regressions: update due to cache latency fix
This commit is contained in:
Nilay Vaish
parent
4920f0d7e5
commit
4646369afd
146 changed files with 38033 additions and 37913 deletions
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@ -1001,6 +1001,7 @@ children=badaddr_responder
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block_size=64
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clock=1000
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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default=system.membus.badaddr_responder.pio
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@ -1026,25 +1027,28 @@ pio=system.membus.default
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[system.physmem]
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type=SimpleDRAM
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activation_limit=4
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addr_mapping=openmap
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banks_per_rank=8
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channels=1
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clock=1000
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conf_table_reported=false
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in_addr_map=true
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lines_per_rowbuffer=64
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mem_sched_policy=fcfs
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lines_per_rowbuffer=32
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mem_sched_policy=frfcfs
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null=false
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page_policy=open
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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tBURST=4000
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tCL=14000
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tRCD=14000
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tBURST=5000
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tCL=13750
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tRCD=13750
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tREFI=7800000
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tRFC=300000
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tRP=14000
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tWTR=1000
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tRP=13750
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tWTR=7500
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tXAW=40000
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write_buffer_size=32
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write_thresh_perc=70
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zero=false
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@ -1073,6 +1077,7 @@ type=CoherentBus
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block_size=64
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clock=500
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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master=system.l2c.cpu_side
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@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 23 2013 13:29:14
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gem5 started Jan 23 2013 13:29:25
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gem5 compiled Mar 26 2013 14:38:52
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gem5 started Mar 26 2013 23:18:50
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 107825000
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Exiting @ tick 1901719660500 because m5_exit instruction encountered
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info: Launching CPU 1 @ 110215000
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Exiting @ tick 1900727015500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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clock=1000
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console=/projects/pd/randd/dist/binaries/console
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console=/scratch/nilay/GEM5/system/binaries/console
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init_param=0
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kernel=/projects/pd/randd/dist/binaries/vmlinux
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/projects/pd/randd/dist/binaries/ts_osfpal
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -520,7 +520,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -540,7 +540,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -615,6 +615,7 @@ type=SimpleDRAM
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activation_limit=4
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addr_mapping=openmap
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banks_per_rank=8
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channels=1
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clock=1000
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conf_table_reported=false
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in_addr_map=true
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@ -646,7 +647,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -1,12 +1,14 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Feb 13 2013 10:45:16
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gem5 started Feb 13 2013 13:46:08
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gem5 executing on u200540-lin
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gem5 compiled Mar 26 2013 14:38:52
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gem5 started Mar 26 2013 23:18:16
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
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info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 1854310111000 because m5_exit instruction encountered
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Exiting @ tick 1854315933000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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clock=1000
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console=/projects/pd/randd/dist/binaries/console
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console=/scratch/nilay/GEM5/system/binaries/console
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init_param=0
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kernel=/projects/pd/randd/dist/binaries/vmlinux
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=atomic
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mem_ranges=0:134217727
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memories=system.physmem
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num_work_ids=16
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pal=/projects/pd/randd/dist/binaries/ts_osfpal
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -581,7 +581,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -601,7 +601,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -698,6 +698,7 @@ type=SimpleDRAM
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activation_limit=4
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addr_mapping=openmap
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banks_per_rank=8
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channels=1
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clock=1000
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conf_table_reported=false
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in_addr_map=true
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@ -729,7 +730,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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image_file=/projects/pd/randd/dist/disks/linux-latest.img
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 23 2013 13:29:14
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gem5 started Jan 23 2013 13:29:38
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gem5 compiled Mar 26 2013 14:38:52
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gem5 started Mar 26 2013 23:27:13
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
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Global frequency set at 1000000000000 ticks per second
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@ -18,204 +18,207 @@ info: Entering event queue @ 1000000000. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 2000000000. Starting simulation...
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info: Entering event queue @ 2000003000. Starting simulation...
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switching cpus
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info: Entering event queue @ 2000001000. Starting simulation...
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info: Entering event queue @ 2000005500. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 3000001000. Starting simulation...
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info: Entering event queue @ 3000043000. Starting simulation...
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info: Entering event queue @ 3000005500. Starting simulation...
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switching cpus
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info: Entering event queue @ 3000047500. Starting simulation...
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info: Entering event queue @ 3000041000. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 4000047500. Starting simulation...
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info: Entering event queue @ 4000041000. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 5000047500. Starting simulation...
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info: Entering event queue @ 5000041000. Starting simulation...
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info: Entering event queue @ 5000053000. Starting simulation...
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switching cpus
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info: Entering event queue @ 5000048000. Starting simulation...
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info: Entering event queue @ 5000056500. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 6000048000. Starting simulation...
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info: Entering event queue @ 7452589500. Starting simulation...
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info: Entering event queue @ 7452657000. Starting simulation...
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info: Entering event queue @ 6000056500. Starting simulation...
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info: Entering event queue @ 7458944500. Starting simulation...
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info: Entering event queue @ 7459012000. Starting simulation...
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switching cpus
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info: Entering event queue @ 7452661500. Starting simulation...
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info: Entering event queue @ 7459016500. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 8452661500. Starting simulation...
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info: Entering event queue @ 8459016500. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 9452661500. Starting simulation...
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info: Entering event queue @ 9452675500. Starting simulation...
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info: Entering event queue @ 9459016500. Starting simulation...
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switching cpus
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info: Entering event queue @ 9452679000. Starting simulation...
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info: Entering event queue @ 9459024000. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 10452679000. Starting simulation...
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info: Entering event queue @ 10459024000. Starting simulation...
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switching cpus
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info: Entering event queue @ 10452682000. Starting simulation...
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info: Entering event queue @ 10459031500. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 11452682000. Starting simulation...
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info: Entering event queue @ 11459031500. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 12452682000. Starting simulation...
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info: Entering event queue @ 12452693500. Starting simulation...
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info: Entering event queue @ 12459031500. Starting simulation...
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info: Entering event queue @ 12459047000. Starting simulation...
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switching cpus
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info: Entering event queue @ 12452696000. Starting simulation...
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info: Entering event queue @ 12459242750. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 13452696000. Starting simulation...
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info: Entering event queue @ 13459242750. Starting simulation...
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info: Entering event queue @ 13459250250. Starting simulation...
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info: Entering event queue @ 13459254000. Starting simulation...
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switching cpus
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info: Entering event queue @ 13452709500. Starting simulation...
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info: Entering event queue @ 13459258500. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 14452709500. Starting simulation...
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info: Entering event queue @ 14459258500. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 15452709500. Starting simulation...
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info: Entering event queue @ 15452713500. Starting simulation...
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info: Entering event queue @ 15459258500. Starting simulation...
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switching cpus
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info: Entering event queue @ 15452714500. Starting simulation...
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info: Entering event queue @ 15459266000. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 16452714500. Starting simulation...
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info: Entering event queue @ 16459266000. Starting simulation...
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switching cpus
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info: Entering event queue @ 16452717000. Starting simulation...
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info: Entering event queue @ 16459273500. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 17452717000. Starting simulation...
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info: Entering event queue @ 17459273500. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 18452717000. Starting simulation...
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info: Entering event queue @ 18452728500. Starting simulation...
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info: Entering event queue @ 18459273500. Starting simulation...
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info: Entering event queue @ 18459284000. Starting simulation...
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switching cpus
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info: Entering event queue @ 18452732000. Starting simulation...
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info: Entering event queue @ 18459287500. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 19452732000. Starting simulation...
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info: Entering event queue @ 19452741000. Starting simulation...
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info: Entering event queue @ 19459287500. Starting simulation...
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switching cpus
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info: Entering event queue @ 19452745500. Starting simulation...
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info: Entering event queue @ 19459295000. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 20452745500. Starting simulation...
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info: Entering event queue @ 20459295000. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 21452745500. Starting simulation...
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info: Entering event queue @ 21459295000. Starting simulation...
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switching cpus
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info: Entering event queue @ 21452746000. Starting simulation...
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info: Entering event queue @ 21459296000. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 22452746000. Starting simulation...
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info: Entering event queue @ 22459296000. Starting simulation...
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switching cpus
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info: Entering event queue @ 22452748000. Starting simulation...
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info: Entering event queue @ 22459303500. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 23452748000. Starting simulation...
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info: Entering event queue @ 23459303500. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 24452748000. Starting simulation...
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info: Entering event queue @ 24459303500. Starting simulation...
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switching cpus
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info: Entering event queue @ 24452750000. Starting simulation...
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info: Entering event queue @ 24459311000. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
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info: Entering event queue @ 25452750000. Starting simulation...
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info: Entering event queue @ 25452773000. Starting simulation...
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info: Entering event queue @ 25459311000. Starting simulation...
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info: Entering event queue @ 25459330000. Starting simulation...
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info: Entering event queue @ 25459339500. Starting simulation...
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info: Entering event queue @ 25459344000. Starting simulation...
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switching cpus
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info: Entering event queue @ 25452778500. Starting simulation...
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info: Entering event queue @ 25459345000. Starting simulation...
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Switching CPUs...
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Next CPU: TimingSimpleCPU
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switching cpus
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info: Entering event queue @ 26452778500. Starting simulation...
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info: Entering event queue @ 26459345000. Starting simulation...
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Switching CPUs...
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Next CPU: DerivO3CPU
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info: Entering event queue @ 27452778500. Starting simulation...
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info: Entering event queue @ 27452782500. Starting simulation...
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info: Entering event queue @ 27459345000. Starting simulation...
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info: Entering event queue @ 27459352500. Starting simulation...
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switching cpus
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info: Entering event queue @ 27452786000. Starting simulation...
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info: Entering event queue @ 27459355500. Starting simulation...
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Switching CPUs...
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Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 28452786000. Starting simulation...
|
||||
info: Entering event queue @ 28452802500. Starting simulation...
|
||||
info: Entering event queue @ 28459355500. Starting simulation...
|
||||
info: Entering event queue @ 28459377000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 28452808000. Starting simulation...
|
||||
info: Entering event queue @ 28459573000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 29452808000. Starting simulation...
|
||||
info: Entering event queue @ 29459573000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 30452808000. Starting simulation...
|
||||
info: Entering event queue @ 30459573000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 30452820500. Starting simulation...
|
||||
info: Entering event queue @ 30459580500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 31452820500. Starting simulation...
|
||||
info: Entering event queue @ 31459580500. Starting simulation...
|
||||
info: Entering event queue @ 31459590000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 31452823500. Starting simulation...
|
||||
info: Entering event queue @ 31459594500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 32452823500. Starting simulation...
|
||||
info: Entering event queue @ 32459594500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 33452823500. Starting simulation...
|
||||
info: Entering event queue @ 33459594500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 33452824500. Starting simulation...
|
||||
info: Entering event queue @ 33459602000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 34452824500. Starting simulation...
|
||||
info: Entering event queue @ 34459602000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 34452827500. Starting simulation...
|
||||
info: Entering event queue @ 34459605000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 35452827500. Starting simulation...
|
||||
info: Entering event queue @ 35459605000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 36452827500. Starting simulation...
|
||||
info: Entering event queue @ 36459605000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 36452828500. Starting simulation...
|
||||
info: Entering event queue @ 36459612500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 37452828500. Starting simulation...
|
||||
info: Entering event queue @ 37459612500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 37452831500. Starting simulation...
|
||||
info: Entering event queue @ 37459615500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 38452831500. Starting simulation...
|
||||
info: Entering event queue @ 38459615500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 39452831500. Starting simulation...
|
||||
info: Entering event queue @ 39459615500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 39452832500. Starting simulation...
|
||||
info: Entering event queue @ 39459623000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 40452832500. Starting simulation...
|
||||
info: Entering event queue @ 40459623000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 40452835500. Starting simulation...
|
||||
info: Entering event queue @ 40459626000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 41452835500. Starting simulation...
|
||||
info: Entering event queue @ 41459626000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 42452835500. Starting simulation...
|
||||
info: Entering event queue @ 42459626000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 42452836500. Starting simulation...
|
||||
info: Entering event queue @ 42459633500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 43452836500. Starting simulation...
|
||||
info: Entering event queue @ 43459633500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 43945335500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -1088,18 +1091,18 @@ Switching CPUs...
|
|||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 304757835500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 304758051500. Starting simulation...
|
||||
info: Entering event queue @ 304757908000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 305758051500. Starting simulation...
|
||||
info: Entering event queue @ 305757908000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 306758051500. Starting simulation...
|
||||
info: Entering event queue @ 306757908000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 307758051500. Starting simulation...
|
||||
info: Entering event queue @ 307757908000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 308593773000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -1968,10 +1971,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 568406273000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 568406301000. Starting simulation...
|
||||
info: Entering event queue @ 568406377000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 569406301000. Starting simulation...
|
||||
info: Entering event queue @ 569406377000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 570312523000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -2156,18 +2159,18 @@ Switching CPUs...
|
|||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 624093773500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 624218766000. Starting simulation...
|
||||
info: Entering event queue @ 624218753000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 625218766000. Starting simulation...
|
||||
info: Entering event queue @ 625218753000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 626218766000. Starting simulation...
|
||||
info: Entering event queue @ 626218753000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 627218766000. Starting simulation...
|
||||
info: Entering event queue @ 627218753000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 627929709000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -2529,10 +2532,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 735398460500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 735398461500. Starting simulation...
|
||||
info: Entering event queue @ 735398468000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 736398461500. Starting simulation...
|
||||
info: Entering event queue @ 736398468000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 737304710500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -2881,10 +2884,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 840867210500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 840867211500. Starting simulation...
|
||||
info: Entering event queue @ 840867218000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 841867211500. Starting simulation...
|
||||
info: Entering event queue @ 841867218000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 842773460500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -3233,10 +3236,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 946335960500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 946335961500. Starting simulation...
|
||||
info: Entering event queue @ 946335968000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 947335961500. Starting simulation...
|
||||
info: Entering event queue @ 947335968000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 948242210500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -3936,49 +3939,49 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1157273460500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1157273461000. Starting simulation...
|
||||
info: Entering event queue @ 1157273468000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1158273461000. Starting simulation...
|
||||
info: Entering event queue @ 1158273468000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1159361004000. Starting simulation...
|
||||
info: Entering event queue @ 1159362057000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1160361004000. Starting simulation...
|
||||
info: Entering event queue @ 1160362057000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1161361004000. Starting simulation...
|
||||
info: Entering event queue @ 1161362057000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1162361004000. Starting simulation...
|
||||
info: Entering event queue @ 1162362057000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1162361007000. Starting simulation...
|
||||
info: Entering event queue @ 1162362060000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1163361007000. Starting simulation...
|
||||
info: Entering event queue @ 1163362060000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1164361007000. Starting simulation...
|
||||
info: Entering event queue @ 1164362060000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1165361007000. Starting simulation...
|
||||
info: Entering event queue @ 1165362060000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1165361010000. Starting simulation...
|
||||
info: Entering event queue @ 1165362063000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1166361010000. Starting simulation...
|
||||
info: Entering event queue @ 1166362063000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1167361010000. Starting simulation...
|
||||
info: Entering event queue @ 1167362063000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1168361010000. Starting simulation...
|
||||
info: Entering event queue @ 1168362063000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1168945335500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -5731,10 +5734,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1694382835500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1694382836500. Starting simulation...
|
||||
info: Entering event queue @ 1694382843000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1695382836500. Starting simulation...
|
||||
info: Entering event queue @ 1695382843000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1696289085500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -5771,10 +5774,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1706101585500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1706101586500. Starting simulation...
|
||||
info: Entering event queue @ 1706101593000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1707101586500. Starting simulation...
|
||||
info: Entering event queue @ 1707101593000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1708007835500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -5900,11 +5903,12 @@ switching cpus
|
|||
info: Entering event queue @ 1744164085500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1745164085500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1745164093000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1746164085500. Starting simulation...
|
||||
info: Entering event queue @ 1746164093000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1747070335500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -5980,10 +5984,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1768601585500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1768601735500. Starting simulation...
|
||||
info: Entering event queue @ 1768601593000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1769601735500. Starting simulation...
|
||||
info: Entering event queue @ 1769601593000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1770507835500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6011,18 +6015,18 @@ Switching CPUs...
|
|||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1777414085500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1777414674000. Starting simulation...
|
||||
info: Entering event queue @ 1777415067000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1778414674000. Starting simulation...
|
||||
info: Entering event queue @ 1778415067000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1779414674000. Starting simulation...
|
||||
info: Entering event queue @ 1779415067000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1780414674000. Starting simulation...
|
||||
info: Entering event queue @ 1780415067000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1781250023000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6033,10 +6037,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1783250023000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1783250024000. Starting simulation...
|
||||
info: Entering event queue @ 1783250030500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1784250024000. Starting simulation...
|
||||
info: Entering event queue @ 1784250030500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1785156273000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6073,10 +6077,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1794968773000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1794968774000. Starting simulation...
|
||||
info: Entering event queue @ 1794968780500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1795968774000. Starting simulation...
|
||||
info: Entering event queue @ 1795968780500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1796875023000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6113,10 +6117,10 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1806687523000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1806687524000. Starting simulation...
|
||||
info: Entering event queue @ 1806687530500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1807687524000. Starting simulation...
|
||||
info: Entering event queue @ 1807687530500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1808593773000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6153,37 +6157,37 @@ Switching CPUs...
|
|||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1818406273000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1818406274000. Starting simulation...
|
||||
info: Entering event queue @ 1818406280500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1819406274000. Starting simulation...
|
||||
info: Entering event queue @ 1819406280500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1819406403500. Starting simulation...
|
||||
info: Entering event queue @ 1819406919000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1820406403500. Starting simulation...
|
||||
info: Entering event queue @ 1820406919000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1821406403500. Starting simulation...
|
||||
info: Entering event queue @ 1821406919000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1821406404500. Starting simulation...
|
||||
info: Entering event queue @ 1821406926500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1822406404500. Starting simulation...
|
||||
info: Entering event queue @ 1822406926500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1822406407500. Starting simulation...
|
||||
info: Entering event queue @ 1822406934000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1823406407500. Starting simulation...
|
||||
info: Entering event queue @ 1823406934000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1824406407500. Starting simulation...
|
||||
info: Entering event queue @ 1824406934000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1825406407500. Starting simulation...
|
||||
info: Entering event queue @ 1825406934000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1826171898000. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6197,21 +6201,22 @@ info: Entering event queue @ 1828171898000. Starting simulation...
|
|||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1829171898000. Starting simulation...
|
||||
info: Entering event queue @ 1829171913500. Starting simulation...
|
||||
info: Entering event queue @ 1829171905500. Starting simulation...
|
||||
info: Entering event queue @ 1829171910500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1829171918000. Starting simulation...
|
||||
info: Entering event queue @ 1829171915000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1830171918000. Starting simulation...
|
||||
info: Entering event queue @ 1830171915000. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1831171918000. Starting simulation...
|
||||
info: Entering event queue @ 1831171915000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1831171920000. Starting simulation...
|
||||
info: Entering event queue @ 1831171922500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1832171920000. Starting simulation...
|
||||
info: Entering event queue @ 1832171922500. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1833007835500. Starting simulation...
|
||||
Switching CPUs...
|
||||
|
|
@ -6234,16 +6239,16 @@ info: Entering event queue @ 1837914085500. Starting simulation...
|
|||
Switching CPUs...
|
||||
Next CPU: DerivO3CPU
|
||||
info: Entering event queue @ 1838914085500. Starting simulation...
|
||||
info: Entering event queue @ 1838914092000. Starting simulation...
|
||||
info: Entering event queue @ 1838914097000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1838914095500. Starting simulation...
|
||||
info: Entering event queue @ 1838914100500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: AtomicSimpleCPU
|
||||
info: Entering event queue @ 1839914095500. Starting simulation...
|
||||
info: Entering event queue @ 1839914105000. Starting simulation...
|
||||
info: Entering event queue @ 1839914100500. Starting simulation...
|
||||
info: Entering event queue @ 1839914110000. Starting simulation...
|
||||
switching cpus
|
||||
info: Entering event queue @ 1839914109500. Starting simulation...
|
||||
info: Entering event queue @ 1839914114500. Starting simulation...
|
||||
Switching CPUs...
|
||||
Next CPU: TimingSimpleCPU
|
||||
switching cpus
|
||||
info: Entering event queue @ 1840914109500. Starting simulation...
|
||||
info: Entering event queue @ 1840914114500. Starting simulation...
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=False
|
||||
|
|
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -65,7 +65,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
|
|
|
|||
|
|
@ -11,24 +11,23 @@ warn: instruction 'mcr icialluis' unimplemented
|
|||
warn: instruction 'mcr dccimvac' unimplemented
|
||||
warn: instruction 'mcr dccmvau' unimplemented
|
||||
warn: instruction 'mcr icimvau' unimplemented
|
||||
warn: 5720641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5728757500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5763076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 5777835500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6298513500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: 5695245000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
|
||||
warn: 5701912500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
|
||||
warn: 5710381500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
|
||||
warn: 5745167500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
|
||||
warn: 5760086500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
|
||||
warn: 6281852500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
|
||||
warn: LCD dual screen mode not supported
|
||||
warn: 52553050000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 2291164927000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: 52533955500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
|
||||
warn: 2291148077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
|
||||
warn: instruction 'mcr icialluis' unimplemented
|
||||
warn: instruction 'mcr bpiallis' unimplemented
|
||||
warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2497502713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2498707539500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2520262039500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2525942762500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2526449392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2527008451000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2527009567500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
warn: 2527556775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
|
||||
warn: 2483713797000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
|
||||
warn: 2498675085000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
|
||||
warn: 2519713161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2520226805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
|
||||
warn: 2525908166000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
|
||||
warn: 2526415429500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
|
||||
warn: 2526974192500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
|
||||
warn: 2526975291500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 25 2013 18:24:48
|
||||
gem5 started Feb 25 2013 22:59:32
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:26:55
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2533144795000 because m5_exit instruction encountered
|
||||
Exiting @ tick 2533114761500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=False
|
||||
|
|
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -65,7 +65,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 25 2013 18:24:48
|
||||
gem5 started Feb 25 2013 23:05:46
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 02:41:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1102934903000 because m5_exit instruction encountered
|
||||
Exiting @ tick 2602778916500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=False
|
||||
|
|
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -65,7 +65,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 25 2013 18:24:48
|
||||
gem5 started Feb 25 2013 22:58:34
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 02:43:56
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2533144795000 because m5_exit instruction encountered
|
||||
Exiting @ tick 2533114761500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=False
|
||||
|
|
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -65,7 +65,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
|
@ -22,5 +23,7 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed.
|
||||
Program aborted at cycle 2395768530500
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=False
|
||||
|
|
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
|
|||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.realview.nvmem system.physmem
|
||||
memories=system.physmem system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
readfile=tests/halt.sh
|
||||
|
|
@ -65,7 +65,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
|
@ -18,3 +19,5 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -13,7 +13,7 @@ atags_addr=256
|
|||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
clock=1000
|
||||
dtb_filename=
|
||||
dtb_filename=False
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
flags_addr=268435504
|
||||
|
|
@ -330,6 +330,7 @@ children=badaddr_responder
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
default=system.membus.badaddr_responder.pio
|
||||
|
|
@ -355,25 +356,28 @@ pio=system.membus.default
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=true
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
@ -503,7 +507,7 @@ warn_access=
|
|||
pio=system.iobus.master[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
type=Pl390
|
||||
clock=1000
|
||||
cpu_addr=520093952
|
||||
cpu_pio_delay=10000
|
||||
|
|
@ -782,6 +786,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: DTB file specified, but no device tree support in kernel
|
||||
warn: The clidr register always reports 0 caches.
|
||||
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
||||
warn: The csselr register isn't implemented.
|
||||
|
|
@ -30,11 +31,3 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -16,7 +16,7 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
|
|
@ -1275,7 +1275,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1295,7 +1295,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:19:51
|
||||
gem5 started Mar 4 2013 00:22:16
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 27 2013 00:32:51
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5132857897000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5132865528000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,6 +179,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -211,6 +212,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:19:12
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -41,4 +41,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 269661304500 because target called exit()
|
||||
Exiting @ tick 269668883500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.269672 # Number of seconds simulated
|
||||
sim_ticks 269671683500 # Number of ticks simulated
|
||||
final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.269669 # Number of seconds simulated
|
||||
sim_ticks 269668883500 # Number of ticks simulated
|
||||
final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 149368 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 149368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66926769 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224496 # Number of bytes of host memory used
|
||||
host_seconds 4029.35 # Real time elapsed on the host
|
||||
host_inst_rate 49435 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 49435 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22150100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271532 # Number of bytes of host memory used
|
||||
host_seconds 12174.61 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
||||
|
|
@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu
|
|||
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 26294 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1014 # Total number of write requests seen
|
||||
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 72 # Tr
|
|||
system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 269671631500 # Total gap between requests
|
||||
system.physmem.totGap 269668831500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1014 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 383646750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 383236250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 580690000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 14598.43 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22096.27 # Average bank access latency per request
|
||||
system.physmem.totBankLat 580676250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 14582.81 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22095.75 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 41694.70 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 41678.56 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -176,36 +176,36 @@ system.physmem.readRowHits 16315 # Nu
|
|||
system.physmem.writeRowHits 296 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9875187.91 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 86405403 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
|
||||
system.physmem.avgGap 9875085.38 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 86401588 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517881 # DTB read hits
|
||||
system.cpu.dtb.read_hits 114517866 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520512 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453501 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 114520497 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39453488 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39455803 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153971382 # DTB hits
|
||||
system.cpu.dtb.write_accesses 39455790 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 153971354 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 153976315 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24997849 # ITB hits
|
||||
system.cpu.dtb.data_accesses 153976287 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 24966979 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 24997871 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 24967001 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -219,34 +219,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 539343368 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 539337768 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 154928367 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 154930401 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.579328 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.579949 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
|
|
@ -258,72 +258,72 @@ system.cpu.committedInsts 601856964 # Nu
|
|||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24996815 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1034 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24965946 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1033 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -332,50 +332,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 178 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 178 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 178 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 178 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 178 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45946500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45946500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45946500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45946500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45946500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45946500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53738.596491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53738.596491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1042 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 22879.137372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21684.500481 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 718.953671 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 475.683220 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
||||
|
|
@ -400,17 +400,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44941500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470659500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 515601000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1197956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1197956000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44941500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1668615500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1713557000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44941500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1668615500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1713557000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -435,17 +435,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53438.168847 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.272727 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103826.218284 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56168.229557 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56168.229557 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65169.126036 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65169.126036 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -467,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34505688 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418277231 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452782919 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932478797 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932478797 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34505688 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350756028 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1385261716 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34505688 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350756028 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1385261716 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -489,51 +489,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41029.355529 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.540848 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91176.584575 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43720.873828 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43720.873828 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786159 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179204 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151786149 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2179214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -550,32 +550,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014154
|
|||
system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -584,14 +584,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -600,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timin
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:43:44
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -41,4 +41,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 133778696500 because target called exit()
|
||||
Exiting @ tick 133696809500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -511,6 +511,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -543,6 +544,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/si
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 19:48:55
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:22:50
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -40,4 +40,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 164543008000 because target called exit()
|
||||
Exiting @ tick 164562530500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -523,6 +523,7 @@ type=SimpleDRAM
|
|||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 13 2013 11:20:14
|
||||
gem5 started Feb 13 2013 14:16:35
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Mar 26 2013 15:04:14
|
||||
gem5 started Mar 26 2013 23:39:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -38,4 +40,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 387315507500 because target called exit()
|
||||
Exiting @ tick 387290918500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/si
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 27 2013 00:17:33
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -42,4 +42,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 607412415000 because target called exit()
|
||||
Exiting @ tick 607388314000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -511,6 +511,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -543,6 +544,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 19:55:20
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:31:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 26773408500 because target called exit()
|
||||
Exiting @ tick 26780899500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 27 2013 00:35:52
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 66030660000 because target called exit()
|
||||
Exiting @ tick 66015916000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -528,9 +528,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:21:53
|
||||
gem5 started Mar 4 2013 00:58:30
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:41:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -67,4 +69,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 199930442500 because target called exit()
|
||||
Exiting @ tick 199986318000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 27 2013 00:05:57
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -81,4 +81,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 434778577000 because target called exit()
|
||||
Exiting @ tick 434516346000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:48:30
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
|
|||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.066667
|
||||
Exiting @ tick 77336466500 because target called exit()
|
||||
Exiting @ tick 77333664500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.077334 # Number of seconds simulated
|
||||
sim_ticks 77333663500 # Number of ticks simulated
|
||||
final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 77333664500 # Number of ticks simulated
|
||||
final_tick 77333664500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 154881 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154881 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31891174 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232452 # Number of bytes of host memory used
|
||||
host_seconds 2424.92 # Real time elapsed on the host
|
||||
host_inst_rate 71983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71983 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 14821773 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278592 # Number of bytes of host memory used
|
||||
host_seconds 5217.57 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 77333595000 # Total gap between requests
|
||||
system.physmem.totGap 77333596000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2084 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
|
||||
|
|
@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 53845750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 53843750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 206982500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 37240000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 115898750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 7229.56 # Average queueing delay per request
|
||||
system.physmem.avgQLat 7229.29 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15561.06 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27790.61 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 27790.35 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -169,14 +169,14 @@ system.physmem.readRowHits 6188 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 10383135.74 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 50250166 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 29237479 # Number of conditional branches predicted
|
||||
system.physmem.avgGap 10383135.88 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 50250164 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 29237478 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25926395 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 25926393 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 89.591056 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 89.591063 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -195,10 +195,10 @@ system.cpu.dtb.data_hits 180219293 # DT
|
|||
system.cpu.dtb.data_misses 79544 # DTB misses
|
||||
system.cpu.dtb.data_acv 48609 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 180298837 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 50219857 # ITB hits
|
||||
system.cpu.itb.fetch_hits 50219856 # ITB hits
|
||||
system.cpu.itb.fetch_misses 371 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 50220228 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 50220227 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -212,26 +212,26 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 154667329 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 154667331 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.icacheStallCycles 51106135 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 448668997 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 50250164 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 78764976 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 19721558 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched
|
||||
system.cpu.fetch.CacheLines 50219856 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 154473494 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75708518 49.01% 49.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -239,41 +239,41 @@ system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Nu
|
|||
system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 35257808 22.82% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154473494 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running
|
||||
system.cpu.decode.IdleCycles 56459568 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 15066335 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74129389 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 9471001 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 4302 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode
|
||||
system.cpu.decode.BranchResolved 9471000 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 4301 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 444763316 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 59590781 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename
|
||||
system.cpu.rename.serializeStallCycles 403368 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 75043533 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 9691219 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 440325289 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups
|
||||
system.cpu.rename.IQFullEvents 19776 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 8008631 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 287258502 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 578891140 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 306269617 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 27726173 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 27858969 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
|
||||
|
|
@ -285,25 +285,25 @@ system.cpu.iq.iqSquashedInstsIssued 966819 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 154473494 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28241556 18.28% 18.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 24263581 15.71% 67.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21289314 13.78% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 8473784 5.49% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154473494 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 34111 0.29% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available
|
||||
|
|
@ -332,7 +332,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5072340 42.83% 74.92% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -372,21 +372,21 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
|
||||
system.cpu.iq.rate 2.597191 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 11841749 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_reads 633918873 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 260111128 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 241419357 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 15066518 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 48930 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 48929 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
|
|
@ -403,7 +403,7 @@ system.cpu.iew.iewDispStoreInsts 80576509 # Nu
|
|||
system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 48930 # Number of memory order violations
|
||||
system.cpu.iew.memOrderViolationEvents 48929 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
|
||||
|
|
@ -418,8 +418,8 @@ system.cpu.iew.exec_stores 78429410 # Nu
|
|||
system.cpu.iew.exec_rate 2.574493 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 193534237 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 193534239 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 271064266 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
|
||||
|
|
@ -427,15 +427,15 @@ system.cpu.iew.wb_penalized_rate 0 # fr
|
|||
system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 149606507 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13038980 8.72% 60.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 11456393 7.66% 68.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 8182424 5.47% 73.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55299800 36.96% 36.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 22506363 15.04% 52.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13038979 8.72% 60.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 8182423 5.47% 73.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle
|
||||
|
|
@ -443,7 +443,7 @@ system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149606500 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149606507 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -456,10 +456,10 @@ system.cpu.commit.int_insts 316365839 # Nu
|
|||
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 557294437 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 557294444 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 870687583 # The number of ROB writes
|
||||
system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 193842 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 193837 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
|
||||
|
|
@ -474,50 +474,50 @@ system.cpu.fp_regfile_writes 104024348 # nu
|
|||
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 2144 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1832.992783 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1832.992784 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 50214379 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12334.654630 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1832.992783 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1832.992784 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 50214380 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 50214380 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 50214380 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 50214380 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 50214380 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50214379 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 50214379 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 50214379 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 50214379 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 50214379 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 50214379 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5477 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 242151500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 242151500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 242151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 242151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 242151500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 242151500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50219857 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50219857 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50219857 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 242149500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 242149500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 242149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 242149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 242149500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 242149500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50219856 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50219856 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50219856 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 50219856 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 50219856 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 50219856 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.433814 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44212.433814 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.068651 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44212.068651 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44212.068651 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44212.068651 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -538,34 +538,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4071
|
|||
system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 185116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 185116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 185116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185114500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 185114500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185114500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 185114500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185114500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 185114500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.997052 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.997052 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.505773 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.505773 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 4012.712247 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 4012.711722 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 372.528715 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2978.555395 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 661.628136 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 372.528717 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2978.554867 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 661.628139 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy
|
||||
|
|
@ -594,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 7448 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7448 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174867500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51533000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 226400500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163361000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163361000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 174867500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 214894000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 389761500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 174867500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 214894000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 389761500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174865500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51532000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 226397500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 174865500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 214892500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 389758000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 174865500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 214892500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 389758000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -629,17 +629,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902460 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.879884 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59852.497096 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52456.093605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.684547 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.684547 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52331.028464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52331.028464 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.301013 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59851.335656 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52455.398517 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.301013 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.305284 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52330.558539 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.301013 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.305284 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52330.558539 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -659,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7448
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131805705 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40944982 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172750687 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998745 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998745 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131805705 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943727 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 297749432 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131805705 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943727 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 297749432 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131803705 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40943982 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172747687 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998245 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998245 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131803705 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165942227 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 297745932 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131803705 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165942227 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 297745932 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -681,37 +681,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38149.263386 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47555.147503 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40025.645737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.199553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.199553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38148.684515 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47553.986063 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.950649 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.039911 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.039911 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 780 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3297.047136 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 159960719 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3297.047137 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 159960717 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 38249.813247 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 38249.812769 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3297.047136 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3297.047137 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86459753 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86459753 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86459751 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86459751 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 159960713 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 159960713 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 159960713 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 159960713 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 159960711 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 159960711 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 159960711 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 159960711 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses
|
||||
|
|
@ -720,24 +720,24 @@ system.cpu.dcache.demand_misses::cpu.data 21580 # n
|
|||
system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 21580 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89990500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 89990500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566610 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 779566610 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 869557110 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 869557110 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 869557110 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 869557110 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86461564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86461564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566110 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 779566110 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 869553610 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 869553610 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 869553610 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 869553610 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86461562 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86461562 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 159982293 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 159982293 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 159982293 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 159982293 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 159982291 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 159982291 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 159982291 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 159982291 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
|
||||
|
|
@ -746,19 +746,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000135
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49691.054666 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49691.054666 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.790784 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.790784 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28158 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.765491 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.765491 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40294.421223 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40294.421223 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28157 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.624406 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.622821 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -780,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4182
|
|||
system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53866000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53866000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221121500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 221121500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221121500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 221121500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -796,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54409.090909 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54409.090909 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -528,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:21:53
|
||||
gem5 started Mar 4 2013 01:05:57
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 03:18:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -13,4 +15,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.060000
|
||||
Exiting @ tick 68244180000 because target called exit()
|
||||
Exiting @ tick 68258363000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-ti
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:57:22
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -1387,4 +1387,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 626365181000 because target called exit()
|
||||
Exiting @ tick 626014950000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -528,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:21:53
|
||||
gem5 started Mar 4 2013 01:12:21
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 02:55:03
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1385,4 +1387,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 627439125000 because target called exit()
|
||||
Exiting @ tick 627426486000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,6 +179,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -211,6 +212,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorde
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:34:49
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 43266024500 because target called exit()
|
||||
Exiting @ tick 42725646500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,61 +1,61 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.042726 # Number of seconds simulated
|
||||
sim_ticks 42726055500 # Number of ticks simulated
|
||||
final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 42725646500 # Number of ticks simulated
|
||||
final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 80618 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 80618 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38990762 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257380 # Number of bytes of host memory used
|
||||
host_seconds 1095.80 # Real time elapsed on the host
|
||||
host_inst_rate 44211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21382391 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280712 # Number of bytes of host memory used
|
||||
host_seconds 1998.17 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165519 # Total number of read requests seen
|
||||
system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 165514 # Total number of read requests seen
|
||||
system.physmem.writeReqs 113997 # Total number of write requests seen
|
||||
system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10593216 # Total number of bytes read from memory
|
||||
system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 10592896 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
|
||||
|
|
@ -76,15 +76,15 @@ system.physmem.perBankWrReqs::13 7250 # Tr
|
|||
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 42726035000 # Total gap between requests
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 42725626000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165519 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165514 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
|
|
@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -124,15 +124,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
|
||||
|
|
@ -147,23 +147,23 @@ system.physmem.wrQLenPdf::19 4956 # Wh
|
|||
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42616.45 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10669.27 # Average bank access latency per request
|
||||
system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 827570000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1763822500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42764.74 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10656.64 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 58285.72 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 58421.38 # Average memory access latency
|
||||
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -171,41 +171,41 @@ system.physmem.avgConsumedWrBW 170.76 # Av
|
|||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 3.27 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.23 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.42 # Average write queue length over time
|
||||
system.physmem.readRowHits 148856 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 71619 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 152857.21 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 18742591 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits
|
||||
system.physmem.avgWrQLen 10.41 # Average write queue length over time
|
||||
system.physmem.readRowHits 148885 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 71702 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 152858.48 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 18741806 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20277550 # DTB read hits
|
||||
system.cpu.dtb.read_hits 20277542 # DTB read hits
|
||||
system.cpu.dtb.read_misses 90148 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20367698 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728779 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 20367690 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14728781 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14736031 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006329 # DTB hits
|
||||
system.cpu.dtb.write_accesses 14736033 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35006323 # DTB hits
|
||||
system.cpu.dtb.data_misses 97400 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35103729 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12368275 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11063 # ITB misses
|
||||
system.cpu.dtb.data_accesses 35103723 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 12368482 # ITB hits
|
||||
system.cpu.itb.fetch_misses 10998 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 12379338 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 12379480 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -219,34 +219,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 85452112 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 85451294 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060657 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 35060353 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 81.422683 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 81.416087 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
||||
system.cpu.comStores 14613377 # Number of Store instructions committed
|
||||
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
||||
|
|
@ -258,194 +258,194 @@ system.cpu.committedInsts 88340673 # Nu
|
|||
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.967293 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.967293 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.033813 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84308 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
|
||||
system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 32800214 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 52651080 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.615310 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 42999576 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 42451718 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 49.679433 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 42421796 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 43029498 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 50.355584 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 63338785 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 22112509 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 25.877325 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 39402182 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 46049112 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.889309 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84283 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.281182 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12251335 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86329 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.914478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12251160 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117106 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.281182 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.931778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.931778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12251335 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 12251335 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 12251335 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 12251335 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 12251335 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 12251335 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 117137 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 117137 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 117137 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 117137 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117137 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117137 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1898913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1898913500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1898913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1898913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1898913500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1898913500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12368472 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12368472 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12368472 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 12368472 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 12368472 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 12368472 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009471 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.009471 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.009471 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.009471 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009471 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009471 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16211.047748 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16211.047748 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16211.047748 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16211.047748 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 46.812500 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336921000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336921000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336921000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1336921000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336921000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1336921000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15481.865345 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15481.865345 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30808 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 30808 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 30808 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 30808 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 30808 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 30808 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86329 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 86329 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 86329 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 86329 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86329 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86329 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336106500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336106500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336106500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1336106500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336106500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1336106500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15476.913899 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15476.913899 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15476.913899 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15476.913899 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15476.913899 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15476.913899 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 131595 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30966.013370 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 131591 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30966.087647 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151345 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163649 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924815 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27281.106918 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513701 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1666.392751 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945008 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79247 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112301 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27282.334509 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2017.545117 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1666.208021 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832591 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061571 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.050849 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.945010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 79227 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 112282 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79247 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 125180 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 79247 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45933 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 125180 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 7107 # number of ReadReq misses
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 79227 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 45934 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 125161 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 79227 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 125161 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 7102 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34628 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34623 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7107 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 7102 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 165519 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 165514 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7102 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996609634 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11996609634 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13509764634 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13965064634 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13509764634 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13965064634 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::total 165514 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454737500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1515184500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1969922000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12017688121 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12017688121 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 454737500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13532872621 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13987610121 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 454737500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13532872621 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13987610121 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86329 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60576 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146905 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 86329 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 290675 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 86329 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 290675 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082267 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454322 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.235683 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91653.434033 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91653.434033 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84371.369051 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84371.369051 # average overall miss latency
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082267 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.569413 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082267 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569413 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64029.498733 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55055.575742 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56896.340583 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91814.472508 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91814.472508 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84510.132804 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84510.132804 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -456,84 +456,84 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7102 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34623 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 165514 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7102 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407373592 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407373592 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578155437 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11945053093 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578155437 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11945053093 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165514 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366405391 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1172806844 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1539212235 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10428442785 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10428442785 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366405391 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11601249629 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11967655020 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366405391 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11601249629 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11967655020 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082267 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454322 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235683 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79511.758578 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79511.758578 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082267 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569413 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082267 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569413 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51591.860180 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42614.979252 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44456.350836 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79672.726047 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79672.726047 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51591.860180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73234.664224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72305.998405 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51591.860180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73234.664224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72305.998405 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200249 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 200250 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.188542 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33754850 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 204346 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.184785 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33754882 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135133 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4078.188542 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20180240 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20180240 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 13574610 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 13574610 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 33754850 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 33754850 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 33754850 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 33754850 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 96398 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 96398 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1038767 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1038767 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1135165 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1135165 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135165 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135165 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3869387500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3869387500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76774000000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 76774000000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 80643387500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 80643387500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 80643387500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 80643387500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -542,56 +542,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 #
|
|||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168350 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168351 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -600,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:35:07
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 24414646000 because target called exit()
|
||||
Exiting @ tick 23931821000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -528,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,11 +1,13 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:21:53
|
||||
gem5 started Mar 4 2013 01:35:26
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 02:50:34
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 25578307500 because target called exit()
|
||||
Exiting @ tick 25534556000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,6 +179,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -211,6 +212,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:29:25
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:56:38
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 985089830500 because target called exit()
|
||||
Exiting @ tick 993429839500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.993559 # Number of seconds simulated
|
||||
sim_ticks 993559170500 # Number of ticks simulated
|
||||
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.993430 # Number of seconds simulated
|
||||
sim_ticks 993429839500 # Number of ticks simulated
|
||||
final_tick 993429839500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 90803 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 90803 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49576515 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449304 # Number of bytes of host memory used
|
||||
host_seconds 20040.92 # Real time elapsed on the host
|
||||
host_inst_rate 61068 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 61068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33337374 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271484 # Number of bytes of host memory used
|
||||
host_seconds 29799.28 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
|
|
@ -16,49 +16,49 @@ system.physmem.bytes_read::cpu.data 125365056 # Nu
|
|||
system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 55340 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 126194172 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 126249512 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 55340 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 55340 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 65586498 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 65586498 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 65586498 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 55340 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 126194172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 191836009 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 1959688 # Total number of read requests seen
|
||||
system.physmem.writeReqs 1018058 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.writeReqs 1018056 # Total number of write requests seen
|
||||
system.physmem.cpureqs 2977747 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 125420032 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
|
||||
system.physmem.bytesWritten 65155584 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q
|
||||
system.physmem.bytesConsumedWr 65155584 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 583 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::0 122178 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 121799 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 121645 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::3 123762 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::4 123293 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::5 122178 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::7 121053 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::8 121197 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::9 121887 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::10 121114 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::12 125176 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::13 123788 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::14 122723 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::15 123934 # Track reads on a per bank basis
|
||||
system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis
|
||||
|
|
@ -73,11 +73,11 @@ system.physmem.perBankWrReqs::10 63292 # Tr
|
|||
system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::14 63646 # Track writes on a per bank basis
|
||||
system.physmem.perBankWrReqs::15 64277 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 993559118500 # Total gap between requests
|
||||
system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 993429787500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -91,11 +91,11 @@ system.physmem.writePktSize::2 0 # Ca
|
|||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::6 1018056 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 1630073 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205372 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 87756 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 35903 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -124,15 +124,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41526 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 43761 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44237 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44257 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44260 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 44261 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 44261 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 44260 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 44260 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
|
||||
|
|
@ -147,65 +147,65 @@ system.physmem.wrQLenPdf::19 44263 # Wh
|
|||
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 18295.82 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29934.69 # Average bank access latency per request
|
||||
system.physmem.wrQLenPdf::23 2738 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 503 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 35756114000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 104195196500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 9795525000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 58643557500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 18251.25 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29933.85 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 53230.51 # Average memory access latency
|
||||
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 53185.10 # Average memory access latency
|
||||
system.physmem.avgRdBW 126.25 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 65.59 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 126.25 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 65.59 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 1.50 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.10 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.46 # Average write queue length over time
|
||||
system.physmem.readRowHits 770937 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
|
||||
system.physmem.avgWrQLen 10.25 # Average write queue length over time
|
||||
system.physmem.readRowHits 770910 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 285915 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 333661.47 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
|
||||
system.physmem.writeRowHitRate 28.08 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 333618.27 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 326686623 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252728421 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138236618 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 220072192 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135769528 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 61.693177 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444796009 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444795652 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449693087 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833358 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 449692730 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833314 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162534662 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605629367 # DTB hits
|
||||
system.cpu.dtb.write_accesses 162534618 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605628966 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612227749 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232025963 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612227348 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 231949721 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 232025985 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 231949743 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -219,34 +219,34 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1986859680 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 172586758 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154099865 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667601840 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043804457 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617884569 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651738878 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617884917 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120537665 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11100495 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131638160 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 83561944 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 61.170119 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 1139346059 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1741702087 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.100705 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7484450 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415164157 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571695523 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.104505 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -258,72 +258,72 @@ system.cpu.committedInsts 1819780127 # Nu
|
|||
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 1.091813 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 1.091813 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.915908 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 0.915908 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 800109422 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186750258 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.729948 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1053226597 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933633083 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.990389 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1014475629 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972384051 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.940751 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1577240024 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409619656 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.616436 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 965534852 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021324828 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.403974 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 667.831181 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 231948615 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270021.670547 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232024854 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1109 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.831181 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.326089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.326089 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 231948615 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 231948615 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 231948615 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 231948615 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 231948615 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 231948615 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1106 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1106 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1106 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1106 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1106 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1106 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 62073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 62073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 62073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 62073500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 62073500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 231949721 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 231949721 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 231949721 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 231949721 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 231949721 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 231949721 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56124.321881 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56124.321881 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56124.321881 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56124.321881 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -332,95 +332,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 65
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 247 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 247 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 247 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 247 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 247 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 247 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51214500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51214500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51214500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51214500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51214500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51214500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59621.071013 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59621.071013 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59621.071013 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59621.071013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59621.071013 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59621.071013 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926957 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30901.189526 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 30901.060234 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958705 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578360 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67146389751 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.225587 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.907127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15830.056812 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.665180 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.911189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15829.483865 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.943029 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044311 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044311 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693293 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693293 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108328 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108328 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7152639 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7152639 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7152639 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7152639 # number of overall hits
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.483078 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.943026 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 6044307 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 6044307 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3693289 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3693289 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108326 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1108326 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7152633 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7152633 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7152633 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7152633 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177530 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178389 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 781299 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 781299 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1177531 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1178390 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 781298 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 781298 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1958829 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1959688 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50226000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163468000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 83213694000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66176738000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 66176738000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 50226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 149340206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 149390432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50226000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 149340206000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 149390432000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50351500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83102971000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 83153322500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66150043000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 66150043000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 50351500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 149253014000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 149303365500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50351500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 149253014000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 149303365500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693293 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693293 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889627 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889627 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3693289 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3693289 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889624 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889624 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111468 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112327 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 9111462 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9112321 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111468 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112327 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111462 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112321 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163051 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
|
||||
|
|
@ -432,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58470.314319 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.349673 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.489122 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84700.912199 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84700.912199 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76231.743012 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76231.743012 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58616.414435 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70573.913553 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70565.197006 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84666.853109 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84666.853109 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58616.414435 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76195.019575 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76187.314256 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58616.414435 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76195.019575 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76187.314256 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -451,30 +451,30 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1018058 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1018056 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1018056 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177530 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178389 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781299 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 781299 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39565474 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68486082132 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68525647606 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56482752358 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56482752358 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39565474 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124968834490 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 125008399964 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39565474 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39688224 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68425761624 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68465449848 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56456219513 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56456219513 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39688224 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124881981137 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 124921669361 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39688224 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124881981137 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 124921669361 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -486,51 +486,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46059.923166 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58160.796015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58151.974947 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72293.388777 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72293.388777 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46202.821886 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58109.520364 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58100.840849 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72259.521352 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72259.521352 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107372 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593512840 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.139102 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9107366 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.260687 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593512555 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.139113 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.260687 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156244082 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156244082 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593512840 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593512840 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593512840 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593512840 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4484420 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11811325 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11811325 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11811325 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11811325 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288000500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 167288000500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 202511222000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 202511222000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156243796 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156243796 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593512555 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593512555 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593512555 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593512555 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4484706 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4484706 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11811610 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11811610 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11811610 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11811610 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 167226851000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 167226851000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 202255523500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 202255523500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 369482374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 369482374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 369482374500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 369482374500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -541,54 +541,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165
|
|||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027902 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027902 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019513 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019513 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019513 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019513 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22823.671635 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22823.671635 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45098.948181 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45098.948181 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31281.288029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31281.288029 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13468960 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4773919 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 372025 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65739 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.204449 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 72.619282 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.writebacks::writebacks 3693289 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693289 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595524 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2595524 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2700148 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2700148 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2700148 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2700148 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150904604500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150904604500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79287604500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79287604500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230192209000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 230192209000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230192209000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 230192209000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -597,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20894.316545 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20894.316545 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41969.277973 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41969.277973 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:57:42
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 22:58:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -25,4 +25,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 655919824500 because target called exit()
|
||||
Exiting @ tick 665534636500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -528,7 +528,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,9 +1,11 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 3 2013 21:21:53
|
||||
gem5 started Mar 4 2013 01:41:28
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 01:49:26
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -24,4 +26,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 517371024000 because target called exit()
|
||||
Exiting @ tick 517355353500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,6 +179,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -211,6 +212,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 13:29:27
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 23:05:23
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
|
||||
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
|
||||
|
|
@ -25,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 41615049000 because target called exit()
|
||||
122 123 124 Exiting @ tick 41622221000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.041622 # Nu
|
|||
sim_ticks 41622221000 # Number of ticks simulated
|
||||
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 75517 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 75517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34200879 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228092 # Number of bytes of host memory used
|
||||
host_seconds 1216.99 # Real time elapsed on the host
|
||||
host_inst_rate 47594 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 47594 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21554846 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275256 # Number of bytes of host memory used
|
||||
host_seconds 1930.99 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca
|
|||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 23405750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 23362750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 74071250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4739.93 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15000.25 # Average bank access latency per request
|
||||
system.physmem.totBankLat 74057500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4731.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14997.47 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24740.18 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 24728.69 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -217,13 +217,13 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
|
|
@ -234,12 +234,12 @@ system.cpu.execution_unit.executions 57404029 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.826152 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 90.826155 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 19996198 # Number of Load instructions committed
|
||||
system.cpu.comStores 6501103 # Number of Store instructions committed
|
||||
system.cpu.comBranches 10240685 # Number of Branches instructions committed
|
||||
|
|
@ -269,16 +269,16 @@ system.cpu.stage2.utilization 59.885481 # Pe
|
|||
system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
|
||||
|
|
@ -293,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 11365 # n
|
|||
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
|
||||
|
|
@ -311,12 +311,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001141
|
|||
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22804.707435 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22804.707435 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -337,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520
|
|||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209599500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209599500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209599500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209599500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209599500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209599500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209587500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209587500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209587500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209587500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209587500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22016.754202 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22016.754202 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22015.493697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22015.493697 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22015.493697 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2190.263404 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2190.263303 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325190 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099202 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
|
||||
|
|
@ -393,17 +393,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132543500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156612500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132531500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24055000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156586500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108217000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240760500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132543500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108217000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240760500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132531500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108203000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240734500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132531500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108203000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240734500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -428,17 +428,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47438.618468 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48697.916667 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47434.323550 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57002.369668 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48689.832090 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48756.682868 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48756.682868 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48751.417578 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47434.323550 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50467.817164 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48751.417578 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -458,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97826921 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18811852 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116638773 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63182194 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63182194 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97826921 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81994046 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179820967 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97826921 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81994046 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179820967 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97814921 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18797852 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116612773 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63183937 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63183937 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97814921 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81981789 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179796710 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97814921 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81981789 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179796710 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -480,25 +480,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35013.214388 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44577.848341 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36268.275187 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36691.169570 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36691.169570 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35008.919470 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44544.672986 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36260.190609 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36692.181765 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36692.181765 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.801521 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801521 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
|
|
@ -517,14 +517,14 @@ system.cpu.dcache.demand_misses::cpu.data 8676 # n
|
|||
system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 8676 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31369500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377432000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377432000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377418000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377418000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377418000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -541,14 +541,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000327
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
|
||||
|
|
@ -575,14 +575,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111258000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111258000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111258000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111258000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -591,14 +591,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -479,6 +479,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -511,6 +512,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 13:29:14
|
||||
gem5 started Jan 23 2013 14:04:24
|
||||
gem5 compiled Mar 26 2013 14:38:52
|
||||
gem5 started Mar 26 2013 23:10:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
|
||||
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||
|
|
@ -25,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 23378067000 because target called exit()
|
||||
122 123 124 Exiting @ tick 23379948000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -511,6 +511,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
|
|
@ -543,6 +544,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleDRAM
|
||||
activation_limit=4
|
||||
addr_mapping=openmap
|
||||
banks_per_rank=8
|
||||
channels=1
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
in_addr_map=true
|
||||
lines_per_rowbuffer=64
|
||||
mem_sched_policy=fcfs
|
||||
lines_per_rowbuffer=32
|
||||
mem_sched_policy=frfcfs
|
||||
null=false
|
||||
page_policy=open
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tBURST=4000
|
||||
tCL=14000
|
||||
tRCD=14000
|
||||
tBURST=5000
|
||||
tCL=13750
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=300000
|
||||
tRP=14000
|
||||
tWTR=1000
|
||||
tRP=13750
|
||||
tWTR=7500
|
||||
tXAW=40000
|
||||
write_buffer_size=32
|
||||
write_thresh_perc=70
|
||||
zero=false
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2013 19:43:25
|
||||
gem5 started Jan 23 2013 21:30:01
|
||||
gem5 compiled Mar 26 2013 15:15:23
|
||||
gem5 started Mar 27 2013 03:01:21
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
|
||||
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
|
||||
|
|
@ -25,4 +25,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 74148853000 because target called exit()
|
||||
122 123 124 Exiting @ tick 74157495500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 11 2013 13:21:48
|
||||
gem5 started Mar 11 2013 13:30:24
|
||||
gem5 compiled Mar 26 2013 15:13:59
|
||||
gem5 started Mar 26 2013 23:44:56
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
|
||||
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
|
||||
|
|
@ -26,4 +26,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 82877188500 because target called exit()
|
||||
122 123 124 Exiting @ tick 82784332500 because target called exit()
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue