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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Nilay Vaish 4646369afd regressions: update due to cache latency fix
2013-03-27 18:36:21 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.400708 # Number of seconds simulated
sim_ticks 2400708253000 # Number of ticks simulated
final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71724 # Simulator instruction rate (inst/s)
host_op_rate 92116 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2854182500 # Simulator tick rate (ticks/s)
host_mem_usage 441348 # Number of bytes of host memory used
host_seconds 841.12 # Real time elapsed on the host
sim_insts 60328852 # Number of instructions simulated
sim_ops 77480507 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 7113744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 84352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 676992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1286200 # Number of bytes read from this memory
system.physmem.bytes_read::total 124661288 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 84352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 764640 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3747008 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory
system.physmem.bytes_written::total 6762824 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 111186 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1318 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20110 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58547 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812501 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47827166 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 209658 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2963186 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 35136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 281997 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 73712 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 535759 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51926879 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 209658 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 35136 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 73712 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 318506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1560793 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 620722 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 83080 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data 552417 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2817012 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1560793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47827166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 209658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3583907 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 35136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 365077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 73712 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1088176 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54743891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 12544378 # Total number of read requests seen
system.physmem.writeReqs 398835 # Total number of write requests seen
system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 802840192 # Total number of bytes read from memory
system.physmem.bytesWritten 25525440 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 102301752 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2640780 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 2352 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 784491 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 784138 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 784232 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 784566 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 784404 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 784106 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 784266 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 784324 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 783997 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 783399 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 783436 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 783681 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 783642 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 783494 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 783837 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 784365 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 24829 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 24774 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 24838 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 24650 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 24877 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 25285 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 25156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 24816 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 24782 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 24769 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 24956 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 24888 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 24972 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry
system.physmem.totGap 2399673084000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 14 # Categorize read packet sizes
system.physmem.readPktSize::3 12509600 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 34764 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 381411 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 17424 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 811080 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 787373 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 793054 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2980679 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2247655 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2247973 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2236496 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 48996 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 48907 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 90849 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 132798 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 90866 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 6937 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 6917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 6892 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 17347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 17345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 17341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 17336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 17328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 17325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 17319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 17315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 17311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17305 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 14410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 14399 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 14391 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 14365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 14363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 14361 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 14359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see
system.physmem.totQLat 275491085000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 350869643750 # Sum of mem lat for all requests
system.physmem.totBusLat 62721890000 # Total cycles spent in databus access
system.physmem.totBankLat 12656668750 # Total cycles spent in bank access
system.physmem.avgQLat 21961.32 # Average queueing delay per request
system.physmem.avgBankLat 1008.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27970.27 # Average memory access latency
system.physmem.avgRdBW 334.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 42.61 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.70 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 0.39 # Average write queue length over time
system.physmem.readRowHits 12490088 # Number of row buffer hits during reads
system.physmem.writeRowHits 392491 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
system.physmem.avgGap 185400.11 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 63256 # number of replacements
system.l2c.tagsinuse 50350.042137 # Cycle average of tags in use
system.l2c.total_refs 1749849 # Total number of references to valid blocks.
system.l2c.sampled_refs 128650 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.601625 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2374435455000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36844.077748 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 5153.281590 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3773.823073 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 798.045066 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 747.763007 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.dtb.walker 4.909443 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.itb.walker 0.003957 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 1438.233653 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 1588.911142 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.562196 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.078633 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.057584 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.012177 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.011410 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.021946 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.024245 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.768281 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 8858 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3206 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 462948 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 169043 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 2530 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 132569 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 65266 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 18106 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 4114 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 284351 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 139144 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1291227 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 597831 # number of Writeback hits
system.l2c.Writeback_hits::total 597831 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 60787 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 19416 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113594 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 8858 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3206 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 462948 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 229830 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 2530 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 132569 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 84682 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 18106 # number of demand (read+write) hits
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system.l2c.overall_mshr_misses::cpu2.dtb.walker 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 2765 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 20688 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 35628 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57085318 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54060944 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 281255 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 146465179 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 123133891 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 381139089 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5113480 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9800980 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 14914460 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313418646 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 730113588 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1043532234 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 57085318 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 367479590 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 281255 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 146465179 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 853247479 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1424671323 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 57085318 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 367479590 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 281255 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 146465179 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 853247479 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1424671323 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25256982500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26555773011 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 51812755511 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 643112863 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9826950545 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 10470063408 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25900095363 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36382723556 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 62282818919 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017966 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.005960 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992172 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984925 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.505782 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.332141 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.352109 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.112582 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.022841 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.022841 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45277.172529 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48458.831562 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 48707.870799 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10085.759369 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.899126 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32458.434756 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40233.294098 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 37533.080387 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 8066044 # DTB read hits
system.cpu0.dtb.read_misses 6218 # DTB read misses
system.cpu0.dtb.write_hits 6637384 # DTB write hits
system.cpu0.dtb.write_misses 2035 # DTB write misses
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 8072262 # DTB read accesses
system.cpu0.dtb.write_accesses 6639419 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 14703428 # DTB hits
system.cpu0.dtb.misses 8253 # DTB misses
system.cpu0.dtb.accesses 14711681 # DTB accesses
system.cpu0.itb.inst_hits 32696148 # ITB inst hits
system.cpu0.itb.inst_misses 3481 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 32699629 # ITB inst accesses
system.cpu0.itb.hits 32696148 # DTB hits
system.cpu0.itb.misses 3481 # DTB misses
system.cpu0.itb.accesses 32699629 # DTB accesses
system.cpu0.numCycles 114001235 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 32202356 # Number of instructions committed
system.cpu0.committedOps 42405748 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37555932 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses
system.cpu0.num_func_calls 1189098 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4237826 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37555932 # number of integer instructions
system.cpu0.num_fp_insts 5136 # number of float instructions
system.cpu0.num_int_register_reads 191328019 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39633304 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written
system.cpu0.num_mem_refs 15368046 # number of memory refs
system.cpu0.num_load_insts 8434010 # Number of load instructions
system.cpu0.num_store_insts 6934036 # Number of store instructions
system.cpu0.num_idle_cycles 13414288023.648659 # Number of idle cycles
system.cpu0.num_busy_cycles -13300286788.648659 # Number of busy cycles
system.cpu0.not_idle_fraction -116.667918 # Percentage of non-idle cycles
system.cpu0.idle_fraction 117.667918 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed
system.cpu0.icache.replacements 892329 # number of replacements
system.cpu0.icache.tagsinuse 511.602586 # Cycle average of tags in use
system.cpu0.icache.total_refs 44224471 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 892841 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 49.532303 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 8120621000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 478.364653 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 17.665639 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst 15.572294 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.934306 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.034503 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst 0.030415 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 32227698 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 8245303 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3751470 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 44224471 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32227698 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 8245303 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3751470 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 44224471 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32227698 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 8245303 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3751470 # number of overall hits
system.cpu0.icache.overall_hits::total 44224471 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 471122 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 134159 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 311537 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 471122 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 134159 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 311537 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 471122 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 134159 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 311537 # number of overall misses
system.cpu0.icache.overall_misses::total 916818 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1808055500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4158384493 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5966439993 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1808055500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4158384493 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5966439993 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1808055500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4158384493 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5966439993 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32698820 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8379462 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4063007 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 45141289 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32698820 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 8379462 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 4063007 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 45141289 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32698820 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 8379462 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 4063007 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 45141289 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014408 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016010 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076676 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.020310 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014408 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016010 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076676 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.020310 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014408 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016010 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076676 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.020310 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.960174 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.963462 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6507.769255 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6507.769255 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6507.769255 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5517 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.292308 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.ReadReq_mshr_hits::total 23964 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 23964 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 23964 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 23964 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 23964 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134159 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287573 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 421732 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 134159 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 287573 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 421732 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 134159 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 287573 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 421732 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3392264993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4932002493 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1539737500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3392264993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4932002493 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1539737500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3392264993 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4932002493 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009342 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009342 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009342 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.636625 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 630023 # number of replacements
system.cpu0.dcache.tagsinuse 511.997115 # Cycle average of tags in use
system.cpu0.dcache.total_refs 23223254 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 630535 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 36.831031 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 495.880002 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 9.605532 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data 6.511582 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.968516 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.018761 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data 0.012718 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6947766 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1882163 # number of ReadReq hits
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system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72982 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 238375 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits
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system.cpu0.dcache.overall_hits::cpu2.data 6603318 # number of overall hits
system.cpu0.dcache.overall_hits::total 22734487 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::total 518872 # number of ReadReq misses
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system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3871 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses
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system.cpu0.dcache.overall_misses::total 1308021 # number of overall misses
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system.cpu0.dcache.WriteReq_miss_latency::total 18721452399 # number of WriteReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52244000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 74787500 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.demand_miss_latency::total 23746252899 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::total 23746252899 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::total 13826146 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35791 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76853 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 250342 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137698 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35791 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73908 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13243484 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 24042508 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13243484 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 3318838 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7480186 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24042508 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023754 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033252 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059861 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.037528 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021563 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217747 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.077244 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046290 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048113 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050369 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047803 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025434 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028420 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117225 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.054405 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025434 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028420 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117225 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.054405 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13946.901356 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14458.566598 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9684.084900 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24614.778758 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30405.136670 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23723.596430 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.463415 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13496.254198 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6249.477730 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18154.336130 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18154.336130 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 8894 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1121 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 44 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.933988 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 20.886364 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 597831 # number of writebacks
system.cpu0.dcache.writebacks::total 597831 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146824 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 146824 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539280 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 539280 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 409 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 409 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 686104 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.ReadReq_mshr_misses::total 202998 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2072752991 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19099500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40608500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59708000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442431500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3199291991 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 4641723491 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442431500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3199291991 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 4641723491 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592956500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28992541000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56585497500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276098000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147117763 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423215763 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28869054500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43139658763 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 72008713263 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033252 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029031 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014682 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021563 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019319 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008035 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048113 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045047 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020708 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011858 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011858 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11946.901356 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12986.778533 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.151775 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22614.778758 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26735.867572 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25250.685139 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.463415 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11729.780474 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11517.746914 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 2162379 # DTB read hits
system.cpu1.dtb.read_misses 2097 # DTB read misses
system.cpu1.dtb.write_hits 1458481 # DTB write hits
system.cpu1.dtb.write_misses 389 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 2164476 # DTB read accesses
system.cpu1.dtb.write_accesses 1458870 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 3620860 # DTB hits
system.cpu1.dtb.misses 2486 # DTB misses
system.cpu1.dtb.accesses 3623346 # DTB accesses
system.cpu1.itb.inst_hits 8379462 # ITB inst hits
system.cpu1.itb.inst_misses 1132 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 8380594 # ITB inst accesses
system.cpu1.itb.hits 8379462 # DTB hits
system.cpu1.itb.misses 1132 # DTB misses
system.cpu1.itb.accesses 8380594 # DTB accesses
system.cpu1.numCycles 573333879 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 8178203 # Number of instructions committed
system.cpu1.committedOps 10418210 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 9330752 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses
system.cpu1.num_func_calls 315480 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1141385 # number of instructions that are conditional controls
system.cpu1.num_int_insts 9330752 # number of integer instructions
system.cpu1.num_fp_insts 1998 # number of float instructions
system.cpu1.num_int_register_reads 53785556 # number of times the integer registers were read
system.cpu1.num_int_register_writes 10103056 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
system.cpu1.num_mem_refs 3793769 # number of memory refs
system.cpu1.num_load_insts 2257716 # Number of load instructions
system.cpu1.num_store_insts 1536053 # Number of store instructions
system.cpu1.num_idle_cycles 537669981.200710 # Number of idle cycles
system.cpu1.num_busy_cycles 35663897.799290 # Number of busy cycles
system.cpu1.not_idle_fraction 0.062204 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.937796 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 4726334 # Number of BP lookups
system.cpu2.branchPred.condPredicted 3843092 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 222010 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 2958856 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2529751 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 85.497604 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 412073 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 21648 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 10884010 # DTB read hits
system.cpu2.dtb.read_misses 22849 # DTB read misses
system.cpu2.dtb.write_hits 3265307 # DTB write hits
system.cpu2.dtb.write_misses 5901 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 675 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 176 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 462 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 10906859 # DTB read accesses
system.cpu2.dtb.write_accesses 3271208 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 14149317 # DTB hits
system.cpu2.dtb.misses 28750 # DTB misses
system.cpu2.dtb.accesses 14178067 # DTB accesses
system.cpu2.itb.inst_hits 4064296 # ITB inst hits
system.cpu2.itb.inst_misses 4509 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 1562 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 968 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 4068805 # ITB inst accesses
system.cpu2.itb.hits 4064296 # DTB hits
system.cpu2.itb.misses 4509 # DTB misses
system.cpu2.itb.accesses 4068805 # DTB accesses
system.cpu2.numCycles 88279018 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9458864 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32433194 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4726334 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 2941824 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 6832879 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1816174 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 51286 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 19337351 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 2080 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 975 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 33815 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 56915 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 312 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 4063011 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 310021 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 1911 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 37021672 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.050656 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.436806 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 30193705 81.56% 81.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 383800 1.04% 82.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 509282 1.38% 83.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 813035 2.20% 86.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 655040 1.77% 87.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 344627 0.93% 88.87% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1013096 2.74% 91.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 238978 0.65% 92.25% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 2870109 7.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 37021672 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.053539 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.367394 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10074280 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 19273281 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 6183203 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 295071 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1194753 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 612486 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 53708 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36748038 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 181597 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1194753 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 10649029 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 6564844 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 11163009 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 5883991 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1564995 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 34501786 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2424 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 422794 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 878812 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents 93 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 37014698 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 157694934 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 157667196 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 27738 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 25798325 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 11216372 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 231057 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 207527 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3357295 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6536002 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3838530 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 533894 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 787090 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 31736542 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 511835 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 34275347 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 54662 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7411950 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 19918044 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 155690 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 37021672 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.925818 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.580792 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 24452597 66.05% 66.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3909614 10.56% 76.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 2349010 6.34% 82.95% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 1972018 5.33% 88.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 2798812 7.56% 95.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 886009 2.39% 98.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 484017 1.31% 99.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 134496 0.36% 99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 35099 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 37021672 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 18701 1.22% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 1408658 91.63% 92.85% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 109949 7.15% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 61376 0.18% 0.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 19371931 56.52% 56.70% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 11383572 33.21% 89.99% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3432179 10.01% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 34275347 # Type of FU issued
system.cpu2.iq.rate 0.388262 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1537308 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.044852 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 107186070 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 39665615 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 27402348 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 6887 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 3783 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3156 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 35747644 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 3635 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 208180 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1582611 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1901 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 9388 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 582353 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5366761 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 352360 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1194753 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 4874895 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 91791 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 32329432 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 60600 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6536002 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3838530 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 369520 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 31433 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2533 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 9388 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 105889 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 88624 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 194513 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 33284218 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 11095059 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 991129 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 81055 # number of nop insts executed
system.cpu2.iew.exec_refs 14494094 # number of memory reference insts executed
system.cpu2.iew.exec_branches 3696710 # Number of branches executed
system.cpu2.iew.exec_stores 3399035 # Number of stores executed
system.cpu2.iew.exec_rate 0.377034 # Inst execution rate
system.cpu2.iew.wb_sent 32864100 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 27405504 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 15677727 # num instructions producing a value
system.cpu2.iew.wb_consumers 28502633 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.310442 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.550045 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 7348668 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 356145 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 169071 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 35826783 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.689728 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.717733 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 27184585 75.88% 75.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4182145 11.67% 87.55% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1258559 3.51% 91.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 654760 1.83% 92.89% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 571167 1.59% 94.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 316320 0.88% 95.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 401210 1.12% 96.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 290625 0.81% 97.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 967412 2.70% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 35826783 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 20002486 # Number of instructions committed
system.cpu2.commit.committedOps 24710742 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8209568 # Number of memory references committed
system.cpu2.commit.loads 4953391 # Number of loads committed
system.cpu2.commit.membars 94240 # Number of memory barriers committed
system.cpu2.commit.branches 3168906 # Number of branches committed
system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 21931175 # Number of committed integer instructions.
system.cpu2.commit.function_calls 294969 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 967412 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 66393860 # The number of ROB reads
system.cpu2.rob.rob_writes 65354684 # The number of ROB writes
system.cpu2.timesIdled 360581 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 51257346 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 3567291742 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 19948293 # Number of Instructions Simulated
system.cpu2.committedOps 24656549 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 19948293 # Number of Instructions Simulated
system.cpu2.cpi 4.425392 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 4.425392 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.225969 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.225969 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 153783407 # number of integer regfile reads
system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes
system.cpu2.misc_regfile_reads 9021581 # number of misc regfile reads
system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 975317722127 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 975317722127 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 975317722127 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 975317722127 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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