826 lines
94 KiB
Plaintext
826 lines
94 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.023380 # Number of seconds simulated
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sim_ticks 23379948000 # Number of ticks simulated
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final_tick 23379948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 61366 # Simulator instruction rate (inst/s)
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host_op_rate 61366 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 17043654 # Simulator tick rate (ticks/s)
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host_mem_usage 277304 # Number of bytes of host memory used
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host_seconds 1371.77 # Real time elapsed on the host
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sim_insts 84179709 # Number of instructions simulated
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sim_ops 84179709 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 195840 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory
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system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 195840 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 195840 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3060 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 8376409 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 5931921 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 14308330 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 8376409 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 8376409 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 8376409 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5931921 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 14308330 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5227 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 5227 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 334528 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 334528 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 327 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 327 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 311 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 286 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 244 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 297 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 281 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 374 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 377 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 354 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 400 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 23379842000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 5227 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 3182 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 29390250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 134711500 # Sum of mem lat for all requests
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system.physmem.totBusLat 26135000 # Total cycles spent in databus access
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system.physmem.totBankLat 79186250 # Total cycles spent in bank access
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system.physmem.avgQLat 5622.78 # Average queueing delay per request
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system.physmem.avgBankLat 15149.46 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 25772.24 # Average memory access latency
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system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.11 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 4448 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 85.10 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 4472898.79 # Average gap between requests
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system.cpu.branchPred.lookups 14842140 # Number of BP lookups
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system.cpu.branchPred.condPredicted 10766991 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 921197 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 8255704 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 6953438 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 84.225864 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1467825 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 3067 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 23110097 # DTB read hits
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system.cpu.dtb.read_misses 194589 # DTB read misses
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system.cpu.dtb.read_acv 2 # DTB read access violations
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system.cpu.dtb.read_accesses 23304686 # DTB read accesses
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system.cpu.dtb.write_hits 7067053 # DTB write hits
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system.cpu.dtb.write_misses 1113 # DTB write misses
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system.cpu.dtb.write_acv 6 # DTB write access violations
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system.cpu.dtb.write_accesses 7068166 # DTB write accesses
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system.cpu.dtb.data_hits 30177150 # DTB hits
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system.cpu.dtb.data_misses 195702 # DTB misses
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system.cpu.dtb.data_acv 8 # DTB access violations
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system.cpu.dtb.data_accesses 30372852 # DTB accesses
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system.cpu.itb.fetch_hits 14723480 # ITB hits
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system.cpu.itb.fetch_misses 97 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 14723577 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 389 # Number of system calls
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system.cpu.numCycles 46759897 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 15452025 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 126885771 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 14842140 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 8421263 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 22118402 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 4462593 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 5523983 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 2725 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 14723480 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 324121 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 46604653 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.722599 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.376512 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 24486251 52.54% 52.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 2361565 5.07% 57.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1190149 2.55% 60.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1742976 3.74% 63.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 2754417 5.91% 69.81% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1149365 2.47% 72.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1217917 2.61% 74.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 773119 1.66% 76.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 10928894 23.45% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 46604653 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.317412 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.713560 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 17272805 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 4225851 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 20520611 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1089695 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 3495691 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 2514029 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 12278 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 123910172 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 32104 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 3495691 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 18413803 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 951839 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 7350 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 20446933 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 3289037 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 121090735 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 399536 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 2410998 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 88918567 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 157348562 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 147674536 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 9674026 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 20491206 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 720 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 712 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 8742624 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 25345876 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 8236695 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2569867 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 913943 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 105383195 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1656 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 96551560 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 178239 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 20729473 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 15559619 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1267 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 46604653 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.071715 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.877215 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 12094878 25.95% 25.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 9328666 20.02% 45.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 8376475 17.97% 63.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 6286526 13.49% 77.43% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4922367 10.56% 87.99% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2863469 6.14% 94.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1727619 3.71% 97.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 799385 1.72% 99.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 205268 0.44% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 46604653 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 187515 11.95% 11.95% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.95% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.95% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 174 0.01% 11.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 7228 0.46% 12.43% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 5644 0.36% 12.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 843061 53.75% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 446254 28.45% 94.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 78748 5.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 58727382 60.82% 60.82% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 479803 0.50% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2798335 2.90% 64.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 115384 0.12% 64.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 2386573 2.47% 66.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 311072 0.32% 67.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 760041 0.79% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 23822951 24.67% 92.59% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 7149693 7.41% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 96551560 # Type of FU issued
|
|
system.cpu.iq.rate 2.064837 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1568624 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.016246 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 226343159 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 117415886 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 87055232 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 15111477 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 8732806 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 7062055 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 90134309 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 7985868 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1517472 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 5349678 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 18734 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 34491 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1735592 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 10525 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1599 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3495691 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 132330 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 18056 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 115618245 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 370442 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 25345876 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 8236695 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1656 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2792 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 34491 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 533607 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 495069 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1028676 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 95323071 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 23305173 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1228489 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 10233394 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 30373541 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 12020857 # Number of branches executed
|
|
system.cpu.iew.exec_stores 7068368 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.038565 # Inst execution rate
|
|
system.cpu.iew.wb_sent 94638543 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 94117287 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 64469301 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 89849772 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.012778 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.717523 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 23716139 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 909447 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 43108962 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.131878 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.747863 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 16687185 38.71% 38.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 9891500 22.95% 61.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4481461 10.40% 72.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2260770 5.24% 77.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1601496 3.71% 81.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1124303 2.61% 83.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 719465 1.67% 85.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 820222 1.90% 87.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5522560 12.81% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 43108962 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 26497301 # Number of memory references committed
|
|
system.cpu.commit.loads 19996198 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 10240685 # Number of branches committed
|
|
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5522560 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 153204556 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 234757733 # The number of ROB writes
|
|
system.cpu.timesIdled 5297 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 155244 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
|
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.555477 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.555477 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.800254 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.800254 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 129030140 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 70506108 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 6188141 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 6043644 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 714512 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 9682 # number of replacements
|
|
system.cpu.icache.tagsinuse 1594.464074 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 14709198 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 11615 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 1266.396728 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1594.464074 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.778547 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.778547 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 14709198 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 14709198 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 14709198 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 14709198 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 14709198 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 14709198 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 14281 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 14281 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 14281 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 14281 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 14281 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 14281 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 321909000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 321909000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 321909000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 321909000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 321909000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 321909000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 14723479 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 14723479 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 14723479 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 14723479 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 14723479 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 14723479 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22541.068553 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 22541.068553 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 22541.068553 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 22541.068553 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2666 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2666 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2666 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2666 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2666 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2666 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11615 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 11615 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 11615 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 11615 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 11615 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 11615 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242799000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 242799000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242799000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 242799000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242799000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 242799000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000789 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000789 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000789 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20903.917348 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20903.917348 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 2409.273789 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 8624 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.402898 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 17.672119 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2009.862780 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 381.738890 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.061336 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.011650 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.073525 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8555 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 8610 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8555 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 8636 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8555 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 8636 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3060 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 462 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3522 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1705 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1705 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3060 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2167 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 5227 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3060 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 5227 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145628500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29406000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 175034500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 86459000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 86459000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 145628500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 115865000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 261493500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 145628500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 115865000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 261493500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11615 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 517 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 12132 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11615 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2248 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 13863 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11615 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2248 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 13863 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.263452 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893617 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.290307 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.263452 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963968 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.377047 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.263452 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.377047 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47591.013072 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63649.350649 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49697.473027 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50709.090909 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50709.090909 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47591.013072 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53467.928011 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 50027.453606 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47591.013072 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53467.928011 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 50027.453606 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3060 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3060 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2167 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3060 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107517341 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23686339 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 131203680 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65625392 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65625392 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107517341 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89311731 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 196829072 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107517341 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89311731 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 196829072 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.263452 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893617 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.290307 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.263452 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.377047 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.263452 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.377047 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35136.385948 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51269.132035 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37252.606474 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38489.965982 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38489.965982 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35136.385948 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41214.458237 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37656.221925 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35136.385948 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41214.458237 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37656.221925 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 159 # number of replacements
|
|
system.cpu.dcache.tagsinuse 1459.922825 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 28072747 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 12487.876779 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 1459.922825 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.356426 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.356426 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 21579507 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 21579507 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 6493005 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 6493005 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 235 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 235 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 28072512 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 28072512 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 28072512 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 28072512 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1007 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1007 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 8098 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 8098 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9105 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9105 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9105 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9105 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 50924000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 50924000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 356653797 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 356653797 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 407577797 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 407577797 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 407577797 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 407577797 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 21580514 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 21580514 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 236 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 28081617 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 28081617 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 28081617 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 28081617 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004237 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004237 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50570.009930 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 50570.009930 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44042.207582 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 44042.207582 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 44764.173202 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 44764.173202 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 14165 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 330 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.924242 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 109 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 491 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 491 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6367 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 6367 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 6858 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 6858 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 6858 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 6858 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 516 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 516 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30419500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30419500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88590998 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 88590998 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119010498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 119010498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119010498 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 119010498 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004237 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004237 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58952.519380 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58952.519380 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51179.086077 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51179.086077 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|