809 lines
92 KiB
Text
809 lines
92 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.077334 # Number of seconds simulated
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sim_ticks 77333664500 # Number of ticks simulated
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final_tick 77333664500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 71983 # Simulator instruction rate (inst/s)
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host_op_rate 71983 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 14821773 # Simulator tick rate (ticks/s)
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host_mem_usage 278592 # Number of bytes of host memory used
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host_seconds 5217.57 # Real time elapsed on the host
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sim_insts 375574808 # Number of instructions simulated
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sim_ops 375574808 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory
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system.physmem.bytes_read::total 476672 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7448 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 476672 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 77333596000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 7448 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2084 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 53843750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 206982500 # Sum of mem lat for all requests
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system.physmem.totBusLat 37240000 # Total cycles spent in databus access
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system.physmem.totBankLat 115898750 # Total cycles spent in bank access
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system.physmem.avgQLat 7229.29 # Average queueing delay per request
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system.physmem.avgBankLat 15561.06 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27790.35 # Average memory access latency
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system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.05 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 6188 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 10383135.88 # Average gap between requests
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system.cpu.branchPred.lookups 50250164 # Number of BP lookups
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system.cpu.branchPred.condPredicted 29237478 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 25926393 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 89.591063 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 101791407 # DTB read hits
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system.cpu.dtb.read_misses 78057 # DTB read misses
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system.cpu.dtb.read_acv 48605 # DTB read access violations
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system.cpu.dtb.read_accesses 101869464 # DTB read accesses
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system.cpu.dtb.write_hits 78427886 # DTB write hits
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system.cpu.dtb.write_misses 1487 # DTB write misses
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system.cpu.dtb.write_acv 4 # DTB write access violations
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system.cpu.dtb.write_accesses 78429373 # DTB write accesses
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system.cpu.dtb.data_hits 180219293 # DTB hits
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system.cpu.dtb.data_misses 79544 # DTB misses
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system.cpu.dtb.data_acv 48609 # DTB access violations
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system.cpu.dtb.data_accesses 180298837 # DTB accesses
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system.cpu.itb.fetch_hits 50219856 # ITB hits
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system.cpu.itb.fetch_misses 371 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 50220227 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numCycles 154667331 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 51106135 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 448668997 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 50250164 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 78764976 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 19721558 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 50219856 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 154473494 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 75708518 49.01% 49.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 35257808 22.82% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 154473494 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 56459568 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 15066335 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 74129389 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 9471000 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 4301 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 444763316 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 59590781 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 403368 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 75043533 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 9691219 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 440325289 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 19776 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 8008631 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 287258502 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 578891140 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 306269617 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 27726173 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 27858969 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 154473494 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 28241556 18.28% 18.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 24263581 15.71% 67.27% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 21289314 13.78% 81.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 8473784 5.49% 96.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 154473494 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 34111 0.29% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 5072340 42.83% 74.92% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
|
|
system.cpu.iq.rate 2.597191 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 11841749 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 633918873 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 260111128 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 241419357 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 15066518 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 48929 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 48929 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 24785465 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 46544583 # Number of branches executed
|
|
system.cpu.iew.exec_stores 78429410 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.574493 # Inst execution rate
|
|
system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 193534239 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 271064266 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 149606507 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 55299800 36.96% 36.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 22506363 15.04% 52.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13038979 8.72% 60.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 8182423 5.47% 73.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 149606507 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
|
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 168275216 # Number of memory references committed
|
|
system.cpu.commit.loads 94754487 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 44587533 # Number of branches committed
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 557294444 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 870687583 # The number of ROB writes
|
|
system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 193837 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
|
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 398027050 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 170092717 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 2144 # number of replacements
|
|
system.cpu.icache.tagsinuse 1832.992784 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 50214379 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 12334.654630 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1832.992784 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 50214379 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 50214379 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 50214379 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 50214379 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 50214379 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 50214379 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5477 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 242149500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 242149500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 242149500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 242149500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 242149500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 242149500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 50219856 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 50219856 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 50219856 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 50219856 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 50219856 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 50219856 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.068651 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 44212.068651 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 44212.068651 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 44212.068651 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 138.400000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1406 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1406 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1406 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1406 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1406 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1406 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4071 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4071 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4071 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185114500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 185114500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185114500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 185114500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185114500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 185114500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.505773 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.505773 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 4012.711722 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 372.528717 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2978.554867 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 661.628139 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.122458 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 616 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 129 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 745 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 657 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 657 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 616 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 189 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 805 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 616 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 189 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 805 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3455 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 861 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4316 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3455 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3993 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7448 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174865500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51532000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 226397500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 174865500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 214892500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 389758000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 174865500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 214892500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 389758000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 657 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 657 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3192 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3192 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4071 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4182 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8253 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4071 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4182 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8253 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.848686 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869697 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.852796 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981203 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981203 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.848686 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.954806 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.902460 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.301013 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59851.335656 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52455.398517 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.301013 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.305284 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52330.558539 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.301013 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.305284 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52330.558539 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3455 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4316 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3455 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3993 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7448 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131803705 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40943982 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172747687 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998245 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998245 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131803705 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165942227 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 297745932 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131803705 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165942227 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 297745932 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981203 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981203 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38148.684515 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47553.986063 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.950649 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.039911 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.039911 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38148.684515 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.283747 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39976.628894 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 780 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3297.047137 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 159960717 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 38249.812769 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3297.047137 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 86459751 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 86459751 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 159960711 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 159960711 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 159960711 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 159960711 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19769 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 21580 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 21580 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566110 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 779566110 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 869553610 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 869553610 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 869553610 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 869553610 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 86461562 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 86461562 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 159982291 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 159982291 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 159982291 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 159982291 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.765491 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.765491 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 40294.421223 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 40294.421223 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 28157 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.622821 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 657 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 657 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16577 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16577 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 17398 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 17398 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 17398 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 17398 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 990 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3192 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3192 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53865000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53865000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221121500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 221121500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221121500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 221121500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54409.090909 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54409.090909 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|