2011-04-25 23:18:08 +02:00
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---------- Begin Simulation Statistics ----------
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2012-05-22 18:38:04 +02:00
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sim_seconds 0.459938 # Number of seconds simulated
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sim_ticks 459937575500 # Number of ticks simulated
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final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-04-25 23:18:08 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-05-22 18:38:04 +02:00
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host_inst_rate 49599 # Simulator instruction rate (inst/s)
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host_op_rate 91715 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 27588814 # Simulator tick rate (ticks/s)
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host_mem_usage 313336 # Number of bytes of host memory used
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host_seconds 16671.16 # Real time elapsed on the host
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2012-02-12 23:07:43 +01:00
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sim_insts 826877144 # Number of instructions simulated
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sim_ops 1528988756 # Number of ops (including micro ops) simulated
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2012-05-22 18:38:04 +02:00
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system.physmem.bytes_read 37483008 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 26316864 # Number of bytes written to this memory
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system.physmem.num_reads 585672 # Number of read requests responded to by this memory
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system.physmem.num_writes 411201 # Number of write requests responded to by this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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2012-05-22 18:38:04 +02:00
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system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 551 # Number of system calls
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2012-05-22 18:38:04 +02:00
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system.cpu.numCycles 919875152 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-05-22 18:38:04 +02:00
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system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits
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2011-04-25 23:18:08 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2012-05-22 18:38:04 +02:00
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system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2012-05-22 18:38:04 +02:00
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system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-05-22 18:38:04 +02:00
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system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 6492696422 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 6491823897 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2012-05-22 18:38:04 +02:00
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system.cpu.iq.issued_per_cycle::0 246353789 27.33% 27.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 156616036 17.37% 44.70% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 150729221 16.72% 61.42% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 147768172 16.39% 77.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2012-05-22 18:38:04 +02:00
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system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-05-22 18:38:04 +02:00
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system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2012-05-22 18:38:04 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued
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2012-02-13 19:30:30 +01:00
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.007566 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 170830738 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 171857297 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.977147 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1379770015 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2939115294 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.committedInsts 826877144 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 533262345 # Number of memory references committed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.loads 384102160 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 149758588 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.rob.rob_reads 2905110180 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4370460169 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedInsts 826877144 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 4004380463 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 262 # number of floating regfile reads
|
|
|
|
|
system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 10653 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 183258482 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 224389 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
|
|
|
|
|
system.cpu.icache.writebacks::total 8 # number of writebacks
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.dcache.replacements 2527239 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 414459202 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 2669585 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 988965 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 988965 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3658550 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3658550 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3658550 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3658550 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39016731000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39016731000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20136479000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 20136479000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 59153210000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 59153210000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 59153210000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 59153210000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 268957551 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2012-01-29 02:09:17 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2012-01-29 02:09:17 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 2229248 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 9153 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 917566 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 917566 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 917566 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 917566 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761172 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1761172 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979812 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 979812 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2740984 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 2740984 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2740984 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 2740984 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14912272500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.l2cache.replacements 574865 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 63.333478 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 7789.592760 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.419945 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001933 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.237720 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.659598 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 6154 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1427336 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1433490 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2229256 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 2229256 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1290 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1290 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 524130 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 524130 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 6154 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1951466 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 1957620 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 6154 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1951466 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 1957620 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 5926 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 332758 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 338684 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 208352 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 208352 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 247027 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 247027 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 5926 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 579785 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 585711 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 5926 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 579785 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 585711 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 203005500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11360844500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 11563850000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9809000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 9809000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8462790000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8462790000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 203005500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 19823634500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 20026640000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 203005500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 19823634500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 20026640000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12080 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1760094 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1772174 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2229256 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 2229256 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209642 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 209642 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771157 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 771157 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-05-22 18:38:04 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 411201 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-25 23:18:08 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
