gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.846145                       # Number of seconds simulated
sim_ticks                                2846145040000                       # Number of ticks simulated
final_tick                               2846145040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 162017                       # Simulator instruction rate (inst/s)
host_op_rate                                   196203                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3671761280                       # Simulator tick rate (ticks/s)
host_mem_usage                                 648900                       # Number of bytes of host memory used
host_seconds                                   775.14                       # Real time elapsed on the host
sim_insts                                   125586921                       # Number of instructions simulated
sim_ops                                     152085297                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1497984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1248876                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8305216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         2560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           388800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           684240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       582144                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12719228                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1497984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       388800                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1886784                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8861888                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8879452                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          130                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             23406                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20035                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       129769                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           40                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6075                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10711                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         9096                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199279                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138467                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142858                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2923                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              526320                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              438796                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2918058                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              136606                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              240409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       204538                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4468932                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         526320                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         136606                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             662926                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3113646                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3119817                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3113646                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2923                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             526320                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             444953                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2918058                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          899                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             136606                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             240423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       204538                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7588749                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199279                       # Number of read requests accepted
system.physmem.writeReqs                       179082                       # Number of write requests accepted
system.physmem.readBursts                      199279                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     179082                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12747712                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9932032                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12719228                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11197788                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23866                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14978                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12467                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12549                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12590                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12626                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14976                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12125                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13379                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13505                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12274                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12440                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11813                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11246                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11354                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11924                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11833                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12082                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9603                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9871                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10084                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9904                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9385                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9666                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10609                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10482                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9764                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9386                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9428                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9248                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9294                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9689                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9592                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9183                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         107                       # Number of times write queue was full causing retry
system.physmem.totGap                    2846144533500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  198700                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 174691                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     98289                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     47643                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7835                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5388                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4763                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4219                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       766                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      254                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1605                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      536                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        91273                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      248.481807                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     139.408554                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     309.811796                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          47817     52.39%     52.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18099     19.83%     72.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6231      6.83%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3556      3.90%     82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2836      3.11%     86.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1554      1.70%     87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          946      1.04%     88.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1020      1.12%     89.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9214     10.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          91273                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6574                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.298296                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      554.918828                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6572     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6574                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6574                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.606328                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.587470                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       41.316435                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            6233     94.81%     94.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              88      1.34%     96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              20      0.30%     96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              23      0.35%     96.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              27      0.41%     97.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             26      0.40%     97.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            23      0.35%     97.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            19      0.29%     98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            11      0.17%     98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             6      0.09%     98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            17      0.26%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            19      0.29%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223             5      0.08%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             3      0.05%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.03%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             1      0.02%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             2      0.03%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             3      0.05%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             5      0.08%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             6      0.09%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             6      0.09%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367             9      0.14%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             2      0.03%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             3      0.05%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             2      0.03%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             3      0.05%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             2      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-655             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             2      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::928-943             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6574                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5766362365                       # Total ticks spent queuing
system.physmem.totMemAccLat                9501043615                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    995915000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28950.07                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47700.07                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.49                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.19                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165729                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97368                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.20                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.73                       # Row buffer hit rate for writes
system.physmem.avgGap                      7522298.90                       # Average gap between requests
system.physmem.pageHitRate                      74.24                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  359432640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  196119000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 812892600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                515833920                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185895971040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83250586485                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634656782000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905687617685                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.569329                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719272584266                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95038840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31827943234                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  330591240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  180382125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 740727000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                489784320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185895971040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82231883055                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635550381500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905419720280                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.475203                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720770086744                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95038840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30336000256                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               33812647                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         16331756                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1585484                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            19439562                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               14041669                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.232435                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               10663467                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            792082                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    65253                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               65253                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        42795                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22458                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        65253                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          65253    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        65253                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6648                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  9627.369284                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  8488.785540                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6159.752779                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6446     96.96%     96.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          188      2.83%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            4      0.06%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            7      0.11%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6648                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      328505000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5136     77.26%     77.26% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1512     22.74%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6648                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65253                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65253                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6648                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6648                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        71901                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    22995822                       # DTB read hits
system.cpu0.dtb.read_misses                     59685                       # DTB read misses
system.cpu0.dtb.write_hits                   17147924                       # DTB write hits
system.cpu0.dtb.write_misses                     5568                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3505                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1156                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1615                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      564                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                23055507                       # DTB read accesses
system.cpu0.dtb.write_accesses               17153492                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         40143746                       # DTB hits
system.cpu0.dtb.misses                          65253                       # DTB misses
system.cpu0.dtb.accesses                     40208999                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3866                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3866                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          306                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3560                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3866                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3866    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3866                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2421                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  9944.030566                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  8839.286720                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5045.849413                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          802     33.13%     33.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1572     64.93%     98.06% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575           10      0.41%     98.47% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2421                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      328041000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2122     87.65%     87.65% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          299     12.35%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2421                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3866                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3866                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2421                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2421                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6287                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    68390761                       # ITB inst hits
system.cpu0.itb.inst_misses                      3866                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2224                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7604                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                68394627                       # ITB inst accesses
system.cpu0.itb.hits                         68390761                       # DTB hits
system.cpu0.itb.misses                           3866                       # DTB misses
system.cpu0.itb.accesses                     68394627                       # DTB accesses
system.cpu0.numCycles                       225488562                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  104715622                       # Number of instructions committed
system.cpu0.committedOps                    126599996                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8092675                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     2098                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5466839701                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.153342                       # CPI: cycles per instruction
system.cpu0.ipc                              0.464394                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2103                       # number of quiesce instructions executed
system.cpu0.tickCycles                      187544415                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       37944147                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           678004                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          485.290770                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           38699274                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           678516                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            57.035168                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        346166500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.290770                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947834                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.947834                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           86                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         80249956                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        80249956                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     21509384                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       21509384                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     16060534                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16060534                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307394                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       307394                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       357644                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       357644                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352742                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       352742                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     37569918                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        37569918                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     37877312                       # number of overall hits
system.cpu0.dcache.overall_hits::total       37877312                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       441440                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       441440                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       555221                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       555221                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131923                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       131923                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20844                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20844                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21317                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21317                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       996661                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        996661                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1128584                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1128584                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5848521453                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5848521453                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8885926805                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8885926805                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    320729731                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    320729731                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    481626159                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    481626159                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       602000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       602000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  14734448258                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14734448258                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  14734448258                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14734448258                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     21950824                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     21950824                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     16615755                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     16615755                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       439317                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       439317                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378488                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       378488                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       374059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       374059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     38566579                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     38566579                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     39005896                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     39005896                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020110                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.020110                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033415                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033415                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300291                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300291                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055072                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055072                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056988                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056988                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025843                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.025843                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028934                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.028934                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       490183                       # number of writebacks
system.cpu0.dcache.writebacks::total           490183                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69583                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        69583                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       243174                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       243174                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14803                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14803                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       312757                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       312757                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       312757                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       312757                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371857                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       371857                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312047                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       312047                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99536                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        99536                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6041                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6041                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21317                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21317                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       683904                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       683904                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       783440                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       783440                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29433                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29433                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26165                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26165                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55598                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55598                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4208861714                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4208861714                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4793451106                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4793451106                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1567109691                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1567109691                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     90045006                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90045006                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    448833841                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    448833841                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       579500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       579500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9002312820                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9002312820                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10569422511                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10569422511                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5627001499                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5627001499                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4261635500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4261635500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9888636999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9888636999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016940                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016940                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018780                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018780                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226570                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226570                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.015961                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.015961                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056988                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056988                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017733                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017733                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020085                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020085                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1884730                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.784347                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           66497574                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1885242                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.272699                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6453364250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.784347                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999579                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999579                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        138650918                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       138650918                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     66497574                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       66497574                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     66497574                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        66497574                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     66497574                       # number of overall hits
system.cpu0.icache.overall_hits::total       66497574                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1885257                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1885257                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1885257                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1885257                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1885257                       # number of overall misses
system.cpu0.icache.overall_misses::total      1885257                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17590953808                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  17590953808                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  17590953808                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  17590953808                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  17590953808                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  17590953808                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     68382831                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     68382831                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     68382831                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     68382831                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     68382831                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     68382831                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027569                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027569                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027569                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027569                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027569                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027569                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9330.798829                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9330.798829                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9330.798829                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9330.798829                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9330.798829                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9330.798829                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1885257                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1885257                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1885257                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1885257                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1885257                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1885257                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  15697482196                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  15697482196                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  15697482196                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  15697482196                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  15697482196                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  15697482196                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027569                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027569                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027569                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027569                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027569                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027569                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8326.441539                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8326.441539                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8326.441539                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8326.441539                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8326.441539                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8326.441539                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1754468                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1754508                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           35                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       221228                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          285273                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16083.611278                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2784455                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          301530                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.234421                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  8638.017947                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.519313                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.077213                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4655.233239                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1567.458030                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1162.305536                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.527223                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003694                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.284133                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.095670                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.070942                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981666                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1030                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15217                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          322                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          428                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          273                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          280                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4109                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7718                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3035                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062866                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.928772                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        52971740                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       52971740                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77753                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4353                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1821437                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       376273                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2279816                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       490181                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       490181                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28296                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28296                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1798                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1798                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212312                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       212312                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77753                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4353                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1821437                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       588585                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2492128                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77753                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4353                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1821437                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       588585                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2492128                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          788                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          123                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        63820                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       101159                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       165890                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        28131                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        28131                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19518                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19518                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43311                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43311                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          788                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          123                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        63820                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144470                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       209201                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          788                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          123                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        63820                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144470                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       209201                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     27073496                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2775500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2907382734                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2926155686                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   5863387416                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    516960426                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    516960426                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    396286408                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    396286408                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       563999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       563999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2178252172                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2178252172                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     27073496                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2775500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2907382734                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5104407858                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8041639588                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     27073496                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2775500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2907382734                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5104407858                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8041639588                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78541                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4476                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1885257                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       477432                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2445706                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       490181                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       490181                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56427                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56427                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21316                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21316                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       255623                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       255623                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78541                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4476                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1885257                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       733055                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2701329                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78541                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4476                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1885257                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       733055                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2701329                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010033                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.027480                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.033852                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.211881                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.067829                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.498538                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.498538                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.915650                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.915650                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169433                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169433                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010033                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.027480                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.033852                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197079                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.077444                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010033                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.027480                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.033852                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197079                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.077444                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34357.228426                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22565.040650                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 45555.981416                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28926.301031                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35345.032347                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18376.894742                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18376.894742                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.638078                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.638078                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       563999                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       563999                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50293.278197                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50293.278197                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34357.228426                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22565.040650                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 45555.981416                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35331.957209                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38439.776043                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34357.228426                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22565.040650                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 45555.981416                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35331.957209                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38439.776043                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       196267                       # number of writebacks
system.cpu0.l2cache.writebacks::total          196267                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           50                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          373                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          423                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2918                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2918                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           50                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3291                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3341                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           50                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3291                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3341                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          788                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          123                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        63770                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       100786                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       165467                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       233242                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       233242                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        28131                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        28131                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19518                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19518                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40393                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        40393                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          788                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          123                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63770                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141179                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       205860                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          788                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          123                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63770                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141179                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       233242                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       439102                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29433                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        32800                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26165                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26165                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55598                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        58965                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21938500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1976000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2484151766                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2249231613                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   4757297879                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14218858632                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14218858632                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    550871371                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    550871371                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    288938194                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    288938194                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       466499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       466499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1582913137                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1582913137                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21938500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1976000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2484151766                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3832144750                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6340211016                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21938500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1976000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2484151766                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3832144750                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14218858632                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  20559069648                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5391279750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5673424250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4065113000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4065113000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9456392750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9738537250                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010033                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.027480                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.033826                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.211100                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.067656                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.498538                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.498538                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.915650                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.915650                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158018                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158018                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010033                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.027480                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.033826                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192590                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076207                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010033                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.027480                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.033826                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192590                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162550                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       466499                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       466499                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2622296                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2539595                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31175                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26165                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       490181                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       288086                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36278                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        93335                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43761                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114801                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       284088                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       269989                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3777247                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2323391                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11902                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       166252                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6278792                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120871872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82524675                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314164                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         203728615                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     661406                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3889209                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.165588                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.371711                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           3245202     83.44%     83.44% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2            644007     16.56%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3889209                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2173439238                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113551498                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2837827806                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1188833142                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7429994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     87720745                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                5430284                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3355584                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           331008                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             3397877                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                2268406                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            66.759509                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 972543                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             68492                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    30040                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               30040                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22353                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7687                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        30040                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          30040    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        30040                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2702                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  9799.871947                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  8761.915074                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6575.386381                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          913     33.79%     33.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1652     61.14%     94.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           67      2.48%     97.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.07%     99.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959            2      0.07%     99.56% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            5      0.19%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            6      0.22%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2702                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1622459264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1622459264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1622459264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         2019     74.72%     74.72% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          683     25.28%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2702                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30040                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30040                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2702                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2702                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        32742                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     5155380                       # DTB read hits
system.cpu1.dtb.read_misses                     27847                       # DTB read misses
system.cpu1.dtb.write_hits                    4232538                       # DTB write hits
system.cpu1.dtb.write_misses                     2193                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2049                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      312                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   511                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      285                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 5183227                       # DTB read accesses
system.cpu1.dtb.write_accesses                4234731                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          9387918                       # DTB hits
system.cpu1.dtb.misses                          30040                       # DTB misses
system.cpu1.dtb.accesses                      9417958                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2268                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2268                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          178                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2090                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2268                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2268    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2268                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1115                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  9869.507623                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  8954.185655                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5421.941384                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          302     27.09%     27.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383          778     69.78%     96.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575            3      0.27%     97.13% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           27      2.42%     99.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959            1      0.09%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            3      0.27%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1115                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1621868264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1621868264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1621868264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          950     85.20%     85.20% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          165     14.80%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1115                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2268                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2268                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1115                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1115                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3383                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    10199097                       # ITB inst hits
system.cpu1.itb.inst_misses                      2268                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1153                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1907                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                10201365                       # ITB inst accesses
system.cpu1.itb.hits                         10199097                       # DTB hits
system.cpu1.itb.misses                           2268                       # DTB misses
system.cpu1.itb.accesses                     10201365                       # DTB accesses
system.cpu1.numCycles                        54377537                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   20871299                       # Number of instructions committed
system.cpu1.committedOps                     25485301                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1815368                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2715                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5637293692                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.605374                       # CPI: cycles per instruction
system.cpu1.ipc                              0.383822                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2716                       # number of quiesce instructions executed
system.cpu1.tickCycles                       38719894                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       15657643                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           231595                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          482.666397                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8898721                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           231963                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.362674                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90493998000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   482.666397                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.942708                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.942708                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          368                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           53                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.718750                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18845353                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18845353                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      4715534                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4715534                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3905905                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3905905                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65439                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        65439                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88128                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        88128                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80091                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        80091                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8621439                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8621439                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8686878                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8686878                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       182965                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       182965                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       168408                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       168408                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35586                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        35586                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17713                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17713                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23494                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23494                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       351373                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        351373                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       386959                       # number of overall misses
system.cpu1.dcache.overall_misses::total       386959                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2670008756                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2670008756                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4196907972                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4196907972                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325609985                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    325609985                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    550485715                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    550485715                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       359500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       359500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6866916728                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6866916728                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6866916728                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6866916728                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4898499                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4898499                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4074313                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4074313                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101025                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       101025                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105841                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       105841                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103585                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       103585                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8972812                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8972812                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      9073837                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      9073837                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037351                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037351                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.041334                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.041334                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.352249                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.352249                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.167355                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.167355                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.226809                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.226809                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.039160                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.039160                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042646                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.042646                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24921.072467                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24921.072467                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18382.543047                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18382.543047                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23430.906402                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23430.906402                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19543.097301                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19543.097301                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       138038                       # number of writebacks
system.cpu1.dcache.writebacks::total           138038                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18091                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        18091                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62532                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        62532                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12272                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12272                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        80623                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        80623                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        80623                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        80623                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       164874                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       164874                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105876                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       105876                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        34136                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        34136                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5441                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5441                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23494                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23494                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       270750                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       270750                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       304886                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       304886                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5716                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5716                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5010                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5010                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10726                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10726                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2161886054                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2161886054                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2482626291                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2482626291                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    533136002                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    533136002                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89692006                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89692006                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    513974285                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    513974285                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       347500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       347500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4644512345                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4644512345                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5177648347                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5177648347                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    978236749                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    978236749                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    848797501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    848797501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1827034250                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1827034250                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033658                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033658                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025986                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025986                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.337897                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.337897                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051407                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051407                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.226809                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.226809                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030174                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.030174                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033601                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033601                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          1038832                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.324542                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            9157675                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          1039344                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             8.811014                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72123856500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.324542                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975243                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975243                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          459                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           53                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         21433382                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        21433382                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      9157675                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        9157675                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      9157675                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         9157675                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      9157675                       # number of overall hits
system.cpu1.icache.overall_hits::total        9157675                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      1039344                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      1039344                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      1039344                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       1039344                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      1039344                       # number of overall misses
system.cpu1.icache.overall_misses::total      1039344                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9221968883                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9221968883                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9221968883                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9221968883                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9221968883                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9221968883                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     10197019                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     10197019                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     10197019                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     10197019                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     10197019                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     10197019                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.101926                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.101926                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.101926                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.101926                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.101926                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.101926                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8872.874508                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8872.874508                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8872.874508                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8872.874508                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8872.874508                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8872.874508                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1039344                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      1039344                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      1039344                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      1039344                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      1039344                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      1039344                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8180244117                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   8180244117                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8180244117                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   8180244117                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8180244117                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   8180244117                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10330000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10330000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10330000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10330000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.101926                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.101926                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.101926                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.101926                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.101926                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.101926                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7870.583865                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7870.583865                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7870.583865                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7870.583865                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7870.583865                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7870.583865                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92232.142857                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       272919                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       272954                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        68790                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           69865                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15664.735857                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1313161                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           84814                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           15.482833                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6115.525293                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    60.132908                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.972099                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5626.461246                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2273.619533                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1588.024777                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.373262                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003670                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000059                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.343412                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.138771                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.096925                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.956100                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1163                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13723                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          666                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          493                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6148                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7266                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.070984                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003845                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.837585                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        25009138                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       25009138                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33079                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2665                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      1011889                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       130945                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1178578                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       138038                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       138038                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1986                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1986                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1041                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total         1041                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38169                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        38169                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33079                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2665                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1011889                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       169114                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1216747                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33079                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2665                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1011889                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       169114                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1216747                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          706                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          219                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        27455                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        73504                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total       101884                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29526                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29526                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22453                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22453                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36197                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        36197                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          706                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          219                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        27455                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       109701                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       138081                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          706                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          219                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        27455                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       109701                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       138081                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17675980                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4473998                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   1080327485                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1722703491                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   2825180954                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    558586766                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    558586766                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449048470                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449048470                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       339500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       339500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1429113805                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1429113805                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17675980                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4473998                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1080327485                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3151817296                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4254294759                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17675980                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4473998                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1080327485                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3151817296                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4254294759                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33785                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2884                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      1039344                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       204449                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1280462                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       138038                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       138038                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31512                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        31512                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23494                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23494                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74366                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        74366                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33785                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2884                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1039344                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       278815                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1354828                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33785                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2884                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1039344                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       278815                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1354828                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020897                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.075936                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.026416                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.359522                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.079568                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.936976                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.936976                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.955691                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.955691                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.486741                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.486741                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020897                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.075936                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026416                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.393454                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.101918                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020897                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.075936                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026416                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.393454                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.101918                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25036.798867                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20429.214612                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 39349.025132                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23436.867259                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27729.387872                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18918.470704                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18918.470704                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19999.486483                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19999.486483                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39481.553858                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39481.553858                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25036.798867                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20429.214612                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39349.025132                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28730.980538                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30810.138679                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25036.798867                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20429.214612                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39349.025132                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28730.980538                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30810.138679                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           82                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    20.500000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        37239                       # number of writebacks
system.cpu1.l2cache.writebacks::total           37239                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst           26                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          127                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          153                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          350                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          350                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           26                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          477                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          503                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           26                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          477                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          503                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          706                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          219                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        27429                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        73377                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total       101731                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35271                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        35271                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29526                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29526                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22453                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22453                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35847                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        35847                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          706                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          219                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27429                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109224                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       137578                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          706                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          219                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27429                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109224                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35271                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       172849                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5716                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5828                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5010                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5010                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10726                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10838                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13073996                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3049500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    898741765                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1240067767                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   2154933028                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1274079828                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1274079828                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    492031029                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    492031029                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    337561796                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    337561796                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       287500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       287500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1155906813                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1155906813                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13073996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3049500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    898741765                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2395974580                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3310839841                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13073996                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3049500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    898741765                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2395974580                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1274079828                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4584919669                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9388000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    932474750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    941862750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    811133499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    811133499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9388000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1743608249                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1752996249                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020897                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.075936                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.026391                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.358901                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.079449                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.936976                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.936976                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.955691                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.955691                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.482035                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.482035                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020897                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.075936                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026391                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.391744                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101546                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020897                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.075936                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026391                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.391744                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.127580                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1679463                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1332654                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        31175                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         5010                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       138038                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        44141                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36278                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        76606                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42998                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89660                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        97798                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        80302                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2078912                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       908693                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7242                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        71512                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3066359                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66525184                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29710243                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       135140                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          96382103                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     669363                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2146516                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.290923                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.454188                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1522045     70.91%     70.91% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2            624471     29.09%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2146516                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     922622470                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     87676498                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1560397383                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    459276108                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4359499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     37739490                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30987                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30987                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72906                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72906                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180818                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483858                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198858516                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36733518                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36403                       # number of replacements
system.iocache.tags.tagsinuse                1.010559                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36419                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270375766000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.010559                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.063160                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.063160                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328077                       # Number of tag accesses
system.iocache.tags.data_accesses              328077                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          229                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              229                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          229                       # number of demand (read+write) misses
system.iocache.demand_misses::total               229                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          229                       # number of overall misses
system.iocache.overall_misses::total              229                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29476377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29476377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6677842621                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6677842621                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29476377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29476377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29476377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29476377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          229                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            229                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          229                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             229                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          229                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            229                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128717.803493                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128717.803493                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128717.803493                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128717.803493                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128717.803493                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         23020                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3484                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.607348                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36174                       # number of writebacks
system.iocache.writebacks::total                36174                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          229                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          229                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          229                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          229                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          229                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          229                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17561377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17561377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4794158657                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4794158657                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17561377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17561377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17561377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17561377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76687.235808                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76687.235808                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   136197                       # number of replacements
system.l2c.tags.tagsinuse                64163.282922                       # Cycle average of tags in use
system.l2c.tags.total_refs                     379817                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   200471                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.894623                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12850.317421                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    69.201711                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.031095                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     6628.601764                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     1957.826461                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32727.538139                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    28.180445                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.851989                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4115.294958                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1518.513926                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4266.925013                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.196080                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001056                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.101144                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.029874                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.499383                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000430                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000013                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.062794                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.023171                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.065108                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.979054                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        30066                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34130                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          141                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5589                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        24336                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           78                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3041                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30776                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.458771                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001190                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.520782                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5295828                       # Number of tag accesses
system.l2c.tags.data_accesses                 5295828                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          375                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           73                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              43717                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              47365                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        45781                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          167                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           27                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              21454                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              10985                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         8059                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 178003                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          233506                       # number of Writeback hits
system.l2c.Writeback_hits::total               233506                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            2927                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             947                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3874                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           249                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            89                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               338                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4056                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2216                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 6272                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           375                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            73                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               43717                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51421                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45781                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           167                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            27                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               21454                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               13201                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         8059                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  184275                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          375                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           73                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              43717                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51421                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45781                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          167                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           27                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              21454                       # number of overall hits
system.l2c.overall_hits::cpu1.data              13201                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         8059                       # number of overall hits
system.l2c.overall_hits::total                 184275                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          130                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            20052                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8676                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       129939                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           40                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5975                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             2283                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         9112                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               176209                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8724                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4132                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12856                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          807                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1210                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2017                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11072                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8457                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19529                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          130                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             20052                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19748                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       129939                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           40                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5975                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10740                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         9112                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195738                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          130                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            20052                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19748                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       129939                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           40                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5975                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10740                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         9112                       # number of overall misses
system.l2c.overall_misses::total               195738                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     10973000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        82500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1610371008                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    763651868                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  13522119331                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      3426000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        83000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    494933758                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    205725771                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   1117904049                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    17729270285                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8986748                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6209345                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     15196093                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1132469                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1093465                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2225934                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1027113188                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    693883201                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1720996389                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     10973000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        82500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1610371008                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1790765056                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13522119331                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      3426000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        83000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    494933758                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    899608972                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1117904049                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19450266674                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     10973000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        82500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1610371008                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1790765056                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13522119331                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      3426000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        83000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    494933758                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    899608972                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1117904049                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19450266674                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          505                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           74                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          63769                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          56041                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       175720                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          207                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           28                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          27429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          13268                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        17171                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             354212                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       233506                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           233506                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11651                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5079                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           16730                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1056                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1299                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2355                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15128                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10673                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25801                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          505                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           74                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           63769                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           71169                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       175720                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          207                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           28                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           27429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           23941                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17171                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              380013                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          505                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           74                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          63769                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          71169                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175720                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          207                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           28                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          27429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          23941                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17171                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             380013                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.257426                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013514                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.314447                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.154815                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.193237                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.035714                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.217835                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.172068                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.497468                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.748777                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.813546                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.768440                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.764205                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.931486                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.856476                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.731888                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.792373                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.756909                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.257426                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.013514                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.314447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.277480                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.193237                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.035714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.217835                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.448603                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.515082                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.257426                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.013514                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.314447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.277480                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.193237                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.035714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.217835                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.448603                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.515082                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84407.692308                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80309.745063                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88018.887506                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        85650                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        83000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82834.101757                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 90112.032852                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 100615.009931                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1030.117836                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1502.745644                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1182.023413                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1403.307311                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   903.690083                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1103.586515                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92766.725795                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82048.386071                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 88125.167136                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84407.692308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80309.745063                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 90680.831274                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        85650                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82834.101757                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83762.474115                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 99368.884294                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84407.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80309.745063                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 90680.831274                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        85650                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82834.101757                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83762.474115                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 99368.884294                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                17                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs            17                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102293                       # number of writebacks
system.l2c.writebacks::total                   102293                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 3                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          130                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        20049                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8676                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       129939                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           40                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5975                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         2283                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         9112                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          176206                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8724                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4132                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12856                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          807                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1210                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2017                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11072                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8457                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19529                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          130                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        20049                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19748                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       129939                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           40                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5975                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10740                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         9112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195735                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          130                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        20049                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19748                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       129939                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           40                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5975                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10740                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         9112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195735                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29433                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5712                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38624                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26165                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5010                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31175                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        55598                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10722                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69799                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9340000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        70000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1359057992                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    655200132                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11920664281                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      2921500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        70500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    420043242                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    177097729                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1006174503                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15550639879                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    155599187                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     74220106                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    229819293                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     14429805                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     21503704                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     35933509                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    890221812                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    588134799                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1478356611                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9340000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1359057992                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1545421944                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11920664281                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2921500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        70500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    420043242                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    765232528                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1006174503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17028996490                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9340000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1359057992                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1545421944                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11920664281                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2921500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        70500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    420043242                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    765232528                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1006174503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17028996490                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4816468250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6816000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    820420250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5848412500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3580583500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    717922501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4298506001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8397051750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6816000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1538342751                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10146918501                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.257426                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013514                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.314400                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.154815                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.193237                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035714                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.217835                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.172068                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.497459                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.748777                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.813546                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.768440                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.764205                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.931486                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.856476                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.731888                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.792373                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.756909                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.257426                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013514                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.314400                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.277480                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.193237                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.035714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.217835                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.448603                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.515074                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.257426                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013514                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.314400                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.277480                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739466                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.193237                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.035714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.217835                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.448603                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.530662                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.515074                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        70500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69544.140830                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75700.579190                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        70500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87000.263060                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        70500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87000.263060                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              215059                       # Transaction distribution
system.membus.trans_dist::ReadResp             215059                       # Transaction distribution
system.membus.trans_dist::WriteReq              31175                       # Transaction distribution
system.membus.trans_dist::WriteResp             31175                       # Transaction distribution
system.membus.trans_dist::Writeback            138467                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            78265                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41611                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15010                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39963                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19392                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14788                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       665413                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       788151                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 897017                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19282584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19476170                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4634432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4634432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24110602                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           126068                       # Total snoops (count)
system.membus.snoop_fanout::samples            580884                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  580884    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              580884                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88642500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            13073499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1170162100                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1173257543                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37390482                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             519203                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            519188                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31175                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31175                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           233506                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36278                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           82002                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41949                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         123951                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51897                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51897                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1081118                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       347519                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1428637                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32891255                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6822675                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39713930                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          293844                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           996034                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.036652                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.187907                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 959527     96.33%     96.33% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36507      3.67%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             996034                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          791138952                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           321000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         673122022                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         273051412                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------