2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.070374 # Number of seconds simulated
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sim_ticks 70374234500 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 169063 # Simulator instruction rate (inst/s)
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host_tick_rate 42767879 # Simulator tick rate (ticks/s)
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host_mem_usage 346452 # Number of bytes of host memory used
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host_seconds 1645.49 # Real time elapsed on the host
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2011-02-05 09:16:09 +01:00
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sim_insts 278192519 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 444 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 140748470 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued
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system.cpu.iq.rate 2.247794 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst)
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|
|
system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 31825957 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 34093246 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.232903 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 232527981 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.count 278192519 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 122219139 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 90779388 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 29309710 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 458749158 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 696922141 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 555004477 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 279973081 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 378 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 284 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 68 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 28269362 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1304 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 2073072 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 83850625 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2506165 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 1447092 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 49070 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2001672 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 76527 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses)
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 29193 # number of writebacks
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
