2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:06 +02:00
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sim_seconds 0.072477 # Number of seconds simulated
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sim_ticks 72477044500 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:06 +02:00
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host_inst_rate 77321 # Simulator instruction rate (inst/s)
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host_tick_rate 20144405 # Simulator tick rate (ticks/s)
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host_mem_usage 388184 # Number of bytes of host memory used
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host_seconds 3597.87 # Real time elapsed on the host
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2011-02-05 09:16:09 +01:00
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sim_insts 278192519 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 444 # Number of system calls
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2011-08-19 22:08:06 +02:00
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system.cpu.numCycles 144954090 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.lookups 38824502 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 38824502 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1297953 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 34176085 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 33665907 # Number of BTB hits
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.icacheStallCycles 29621269 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 208413424 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 38824502 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 33665907 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 64871665 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 11337306 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 39226989 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 173 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 28797824 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 223613 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 143548717 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.559587 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.289378 # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::0 81263708 56.61% 56.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3814966 2.66% 59.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2940174 2.05% 61.32% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4531865 3.16% 64.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 6958174 4.85% 69.32% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 5381940 3.75% 73.07% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 7686471 5.35% 78.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4497983 3.13% 81.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 26473436 18.44% 100.00% # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::total 143548717 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.267840 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.437789 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 42470221 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 29708132 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 53823823 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 7717953 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9828588 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 362980420 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 9828588 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 49423752 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 5177939 # Number of cycles rename is blocking
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.serializeStallCycles 6920 # count of cycles rename stalled for serializing inst
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.RunCycles 54367682 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 24743836 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 358046310 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 26 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 279275 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 20623155 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 321830310 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 881760386 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 881756685 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 3701 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.UndoneMaps 73486118 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 57368685 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 115894254 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 38422039 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 63771824 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 11957885 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 350732960 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 318496999 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 118138 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 72405796 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 110903478 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 143548717 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.218738 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.761833 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::0 32402965 22.57% 22.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 21621693 15.06% 37.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 28790762 20.06% 57.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 27748357 19.33% 77.02% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 16847570 11.74% 88.76% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 10612221 7.39% 96.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 3153195 2.20% 98.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 2297476 1.60% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 74478 0.05% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::total 143548717 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.fu_full::IntAlu 25496 0.77% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 3039528 91.70% 92.47% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 249529 7.53% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.FU_type_0::IntAlu 181568475 57.01% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 37 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 102910190 32.31% 89.32% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 34001586 10.68% 100.00% # Type of FU issued
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.FU_type_0::total 318496999 # Type of FU issued
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system.cpu.iq.rate 2.197227 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 3314553 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010407 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 783974996 # Number of integer instruction queue reads
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|
|
system.cpu.iq.int_inst_queue_writes 423448386 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 314158938 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 410 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 2380 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 321794634 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 207 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 44143933 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 25114866 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7244 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 332312 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 6982288 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3439 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 14779 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 9828588 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 873179 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 111050 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 350733425 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 18952 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 115894254 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 38422039 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 328 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 81820 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 332312 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1218982 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 194001 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1412983 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 316233239 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 102244590 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2263760 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.exec_refs 135866033 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 31754283 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 33621443 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.181610 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 314904091 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 314159101 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 236907780 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 336010619 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.wb_rate 2.167301 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.705060 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 72547467 # The number of squashed insts skipped by commit
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.branchMispredicts 1297979 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 133720129 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.080409 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.620850 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 52184328 39.03% 39.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 25094085 18.77% 57.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 17016190 12.73% 70.52% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12703052 9.50% 80.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 3715852 2.78% 82.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 3516909 2.63% 85.42% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 3092720 2.31% 87.74% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1223319 0.91% 88.65% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 15173674 11.35% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 133720129 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.count 278192519 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 122219139 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 90779388 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 29309710 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.bw_lim_events 15173674 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.rob.rob_reads 469286441 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 711329741 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 41147 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 1405373 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.cpi 0.521057 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.521057 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.919177 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.919177 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 555871897 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 282032504 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 111 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 126 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 202657544 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 67 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 826.564016 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 28796514 # Total number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.avg_refs 27984.950437 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 826.564016 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.403596 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 28796514 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 28796514 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 28796514 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1310 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1310 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1310 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 47269000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 47269000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 47269000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 28797824 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 28797824 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 28797824 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 36083.206107 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 36083.206107 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 36083.206107 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 1030 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 1030 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 1030 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 36240000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 36240000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 36240000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35184.466019 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35184.466019 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35184.466019 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.replacements 2072715 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4076.040338 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 86994905 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2076811 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 41.888696 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 24878005000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4076.040338 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.995127 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 55797094 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 31197802 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 86994896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 86994896 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 2231267 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 241949 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 2473216 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2473216 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 14264095500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 4347965193 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 18612060693 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 18612060693 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 58028361 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_accesses 89468112 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 89468112 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.038451 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.007696 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.027644 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.027644 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 6392.823226 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 17970.585508 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 7525.448927 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 7525.448927 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 284000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 84 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3380.952381 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.writebacks 1447001 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 260149 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 136252 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 396401 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 396401 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1971118 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 105697 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2076815 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2076815 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5560817000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1877216693 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 7438033693 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 7438033693 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.033968 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003362 # mshr miss rate for WriteReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.023213 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.023213 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2821.148708 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17760.359263 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 3581.461850 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 3581.461850 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.replacements 49102 # number of replacements
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 18748.930580 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3317286 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 77110 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 43.020179 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 6700.733856 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 12048.196724 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.204490 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.367682 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1937583 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1447001 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 63701 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 2001284 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2001284 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 34508 # number of ReadReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 42051 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 76559 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 76559 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1180262000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1442869500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 2623131500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 2623131500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1972091 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1447001 # number of Writeback accesses(hits+misses)
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 105752 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 2077843 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 2077843 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.017498 # miss rate for ReadReq accesses
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.397638 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.036845 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.036845 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34202.561725 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.370693 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34262.875691 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34262.875691 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.writebacks 29193 # number of writebacks
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 34508 # number of ReadReq MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 42051 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 76559 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 76559 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1070240500 # number of ReadReq MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1310019500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2380260000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2380260000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017498 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.397638 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.036845 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.036845 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31014.272053 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31153.111698 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31090.531486 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31090.531486 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
