2005-02-26 00:00:49 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2005 The Regents of The University of Michigan
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2005-02-26 00:00:49 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2006-04-23 00:45:01 +02:00
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#ifndef __CPU_OZONE_CPU_HH__
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#define __CPU_OZONE_CPU_HH__
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#include <set>
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2005-02-26 00:00:49 +01:00
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#include "base/statistics.hh"
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2006-04-23 00:45:01 +02:00
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#include "base/timebuf.hh"
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2005-08-30 19:18:54 +02:00
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#include "config/full_system.hh"
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2005-06-05 02:50:10 +02:00
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#include "cpu/base.hh"
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2005-02-26 00:00:49 +01:00
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#include "cpu/exec_context.hh"
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2006-04-23 00:45:01 +02:00
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/ozone/thread_state.hh"
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2005-02-26 00:00:49 +01:00
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "mem/mem_interface.hh"
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#include "sim/eventq.hh"
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// forward declarations
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2005-08-30 19:18:54 +02:00
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#if FULL_SYSTEM
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2006-04-23 00:45:01 +02:00
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#include "arch/alpha/tlb.hh"
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2005-02-26 00:00:49 +01:00
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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2006-04-23 00:45:01 +02:00
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class MemoryController;
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2005-02-26 00:00:49 +01:00
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class RemoteGDB;
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class GDBListener;
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#else
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2006-04-23 00:45:01 +02:00
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class PageTable;
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2005-02-26 00:00:49 +01:00
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class Process;
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#endif // FULL_SYSTEM
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class Checkpoint;
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class MemInterface;
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namespace Trace {
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class InstRecord;
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}
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/**
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* Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
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* simple out-of-order capabilities added to it. It is still a 1 CPI machine
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* (?), but is capable of handling cache misses. Basically it models having
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* a ROB/IQ by only allowing a certain amount of instructions to execute while
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* the cache miss is outstanding.
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*/
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template <class Impl>
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2006-04-23 00:45:01 +02:00
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class OzoneCPU : public BaseCPU
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2005-02-26 00:00:49 +01:00
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{
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private:
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2006-04-23 00:45:01 +02:00
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typedef typename Impl::FrontEnd FrontEnd;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::DynInst DynInst;
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2005-02-26 00:00:49 +01:00
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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2006-04-23 00:45:01 +02:00
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typedef TheISA::MiscReg MiscReg;
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public:
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class OzoneXC : public ExecContext {
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public:
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OzoneCPU<Impl> *cpu;
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OzoneThreadState<Impl> *thread;
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BaseCPU *getCpuPtr();
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void setCpuId(int id);
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int readCpuId() { return thread->cpuId; }
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FunctionalMemory *getMemPtr() { return thread->mem; }
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#if FULL_SYSTEM
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System *getSystemPtr() { return cpu->system; }
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PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
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AlphaITB *getITBPtr() { return cpu->itb; }
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AlphaDTB * getDTBPtr() { return cpu->dtb; }
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#else
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Process *getProcessPtr() { return thread->process; }
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#endif
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Status status() const { return thread->_status; }
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void setStatus(Status new_status);
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Unallocated.
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void deallocate();
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/// Set the status to Halted.
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void halt();
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#if FULL_SYSTEM
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void dumpFuncProfile();
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#endif
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void takeOverFrom(ExecContext *old_context);
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void regStats(const std::string &name);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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Event *getQuiesceEvent();
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Tick readLastActivate();
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Tick readLastSuspend();
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void profileClear();
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void profileSample();
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#endif
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int getThreadNum();
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// Also somewhat obnoxious. Really only used for the TLB fault.
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TheISA::MachInst getInst();
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void copyArchRegs(ExecContext *xc);
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void clearArchRegs();
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uint64_t readIntReg(int reg_idx);
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float readFloatRegSingle(int reg_idx);
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double readFloatRegDouble(int reg_idx);
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uint64_t readFloatRegInt(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatRegSingle(int reg_idx, float val);
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void setFloatRegDouble(int reg_idx, double val);
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void setFloatRegInt(int reg_idx, uint64_t val);
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uint64_t readPC() { return thread->PC; }
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void setPC(Addr val);
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uint64_t readNextPC() { return thread->nextPC; }
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void setNextPC(Addr val);
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public:
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// ISA stuff:
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MiscReg readMiscReg(int misc_reg);
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
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Fault setMiscReg(int misc_reg, const MiscReg &val);
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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bool inPalMode() { return cpu->inPalMode(); }
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#endif
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bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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{ return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
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// used to shift args for indirect syscall
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void setSyscallArg(int i, TheISA::IntReg val)
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{ thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
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void setSyscallReturn(SyscallReturn return_value)
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{ cpu->setSyscallReturn(return_value, thread->tid); }
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Counter readFuncExeInst() { return thread->funcExeInst; }
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void setFuncExeInst(Counter new_val)
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{ thread->funcExeInst = new_val; }
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#endif
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};
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// execution context proxy
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OzoneXC xcProxy;
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typedef OzoneThreadState<Impl> ImplState;
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private:
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OzoneThreadState<Impl> thread;
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/*
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// Squash event for when the XC needs to squash all inflight instructions.
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struct XCSquashEvent : public Event
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{
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void process();
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const char *description();
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};
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*/
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2005-02-26 00:00:49 +01:00
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public:
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// main simulation loop (one cycle)
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void tick();
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2006-04-23 00:45:01 +02:00
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std::set<InstSeqNum> snList;
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2005-02-26 00:00:49 +01:00
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private:
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struct TickEvent : public Event
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{
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2006-04-23 00:45:01 +02:00
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OzoneCPU *cpu;
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2005-02-26 00:00:49 +01:00
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int width;
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2006-04-23 00:45:01 +02:00
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TickEvent(OzoneCPU *c, int w);
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2005-02-26 00:00:49 +01:00
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + delay);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + delay);
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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private:
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Trace::InstRecord *traceData;
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template<typename T>
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void trace_data(T data);
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public:
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//
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enum Status {
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Running,
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Idle,
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SwitchedOut
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};
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Status _status;
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public:
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2006-04-23 00:45:01 +02:00
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bool checkInterrupts;
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2005-02-26 00:00:49 +01:00
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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2006-04-23 00:45:01 +02:00
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typedef typename Impl::Params Params;
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2005-02-26 00:00:49 +01:00
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2006-04-23 00:45:01 +02:00
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OzoneCPU(Params *params);
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2005-02-26 00:00:49 +01:00
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2006-04-23 00:45:01 +02:00
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virtual ~OzoneCPU();
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2005-02-26 00:00:49 +01:00
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2005-05-03 16:56:47 +02:00
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void init();
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2005-02-26 00:00:49 +01:00
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public:
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2006-04-23 00:45:01 +02:00
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BaseCPU *getCpuPtr() { return this; }
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void setCpuId(int id) { cpuId = id; }
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int readCpuId() { return cpuId; }
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// FunctionalMemory *getMemPtr() { return mem; }
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int cpuId;
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2005-02-26 00:00:49 +01:00
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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2005-08-30 19:18:54 +02:00
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#if FULL_SYSTEM
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2005-02-26 00:00:49 +01:00
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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2006-04-23 00:45:01 +02:00
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AlphaITB *itb;
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AlphaDTB *dtb;
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System *system;
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// the following two fields are redundant, since we can always
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// look them up through the system pointer, but we'll leave them
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// here for now for convenience
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MemoryController *memctrl;
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PhysicalMemory *physmem;
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2005-02-26 00:00:49 +01:00
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#endif
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// L1 instruction cache
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MemInterface *icacheInterface;
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// L1 data cache
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MemInterface *dcacheInterface;
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2006-04-23 00:45:01 +02:00
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#if !FULL_SYSTEM
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PageTable *pTable;
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#endif
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2005-02-26 00:00:49 +01:00
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2006-04-23 00:45:01 +02:00
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FrontEnd *frontEnd;
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2005-05-03 16:56:47 +02:00
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2006-04-23 00:45:01 +02:00
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BackEnd *backEnd;
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2005-05-03 16:56:47 +02:00
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private:
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2005-02-26 00:00:49 +01:00
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Status status() const { return _status; }
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2006-04-23 00:45:01 +02:00
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void setStatus(Status new_status) { _status = new_status; }
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// Not sure what an activate() call on the CPU's proxy XC would mean...
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2005-02-26 00:00:49 +01:00
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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2006-04-23 00:45:01 +02:00
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public:
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2005-02-26 00:00:49 +01:00
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Counter numInst;
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Counter startNumInst;
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2006-04-23 00:45:01 +02:00
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// Stats::Scalar<> numInsts;
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2005-02-26 00:00:49 +01:00
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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2006-04-23 00:45:01 +02:00
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private:
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2005-02-26 00:00:49 +01:00
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// number of simulated memory references
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2006-04-23 00:45:01 +02:00
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// Stats::Scalar<> numMemRefs;
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2005-02-26 00:00:49 +01:00
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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2005-05-03 16:56:47 +02:00
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public:
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2005-02-26 00:00:49 +01:00
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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2006-04-23 00:45:01 +02:00
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2005-08-30 19:18:54 +02:00
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#if FULL_SYSTEM
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2005-02-26 00:00:49 +01:00
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bool validInstAddr(Addr addr) { return true; }
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bool validDataAddr(Addr addr) { return true; }
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2006-02-22 02:10:40 +01:00
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Fault translateInstReq(MemReqPtr &req)
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2005-02-26 00:00:49 +01:00
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{
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return itb->translate(req);
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}
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|
2006-02-22 02:10:40 +01:00
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Fault translateDataReadReq(MemReqPtr &req)
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2005-02-26 00:00:49 +01:00
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{
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return dtb->translate(req, false);
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}
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|
2006-02-22 02:10:40 +01:00
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Fault translateDataWriteReq(MemReqPtr &req)
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2005-02-26 00:00:49 +01:00
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{
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return dtb->translate(req, true);
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}
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#else
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bool validInstAddr(Addr addr)
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2006-04-23 00:45:01 +02:00
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{ return true; }
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2005-02-26 00:00:49 +01:00
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bool validDataAddr(Addr addr)
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2006-04-23 00:45:01 +02:00
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{ return true; }
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2005-02-26 00:00:49 +01:00
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2006-04-23 00:45:01 +02:00
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int getInstAsid() { return thread.asid; }
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int getDataAsid() { return thread.asid; }
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2005-02-26 00:00:49 +01:00
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2006-02-22 02:10:40 +01:00
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Fault dummyTranslation(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
|
Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 07:22:51 +01:00
|
|
|
return NoFault;
|
2005-02-26 00:00:49 +01:00
|
|
|
}
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
/** Translates instruction requestion in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateInstReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return dummyTranslation(req);
|
|
|
|
}
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
/** Translates data read request in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataReadReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return dummyTranslation(req);
|
|
|
|
}
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
/** Translates data write request in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataWriteReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return dummyTranslation(req);
|
|
|
|
}
|
|
|
|
#endif
|
2006-04-23 00:45:01 +02:00
|
|
|
/** CPU read function, forwards read to LSQ. */
|
2005-02-26 00:00:49 +01:00
|
|
|
template <class T>
|
2006-04-23 00:45:01 +02:00
|
|
|
Fault read(MemReqPtr &req, T &data, int load_idx)
|
|
|
|
{
|
|
|
|
return backEnd->read(req, data, load_idx);
|
|
|
|
}
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
/** CPU write function, forwards write to LSQ. */
|
2005-02-26 00:00:49 +01:00
|
|
|
template <class T>
|
2006-04-23 00:45:01 +02:00
|
|
|
Fault write(MemReqPtr &req, T &data, int store_idx)
|
|
|
|
{
|
|
|
|
return backEnd->write(req, data, store_idx);
|
|
|
|
}
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
void prefetch(Addr addr, unsigned flags)
|
|
|
|
{
|
|
|
|
// need to do this...
|
|
|
|
}
|
|
|
|
|
|
|
|
void writeHint(Addr addr, int size, unsigned flags)
|
|
|
|
{
|
|
|
|
// need to do this...
|
|
|
|
}
|
|
|
|
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault copySrcTranslate(Addr src);
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault copy(Addr dest);
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
InstSeqNum globalSeqNum;
|
|
|
|
|
|
|
|
public:
|
2006-04-23 00:45:01 +02:00
|
|
|
void squashFromXC();
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
// @todo: This can be a useful debug function. Implement it.
|
|
|
|
void dumpInsts() { frontEnd->dumpInsts(); }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2005-08-30 19:18:54 +02:00
|
|
|
#if FULL_SYSTEM
|
2006-04-23 00:45:01 +02:00
|
|
|
Fault hwrei();
|
|
|
|
int readIntrFlag() { return thread.regs.intrflag; }
|
|
|
|
void setIntrFlag(int val) { thread.regs.intrflag = val; }
|
|
|
|
bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
|
|
|
|
bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
|
|
|
|
bool simPalCheck(int palFunc);
|
2005-02-26 00:00:49 +01:00
|
|
|
#else
|
2006-04-23 00:45:01 +02:00
|
|
|
void syscall();
|
|
|
|
void setSyscallReturn(SyscallReturn return_value, int tid);
|
2005-02-26 00:00:49 +01:00
|
|
|
#endif
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
ExecContext *xcBase() { return &xcProxy; }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
bool decoupledFrontEnd;
|
|
|
|
struct CommStruct {
|
|
|
|
InstSeqNum doneSeqNum;
|
|
|
|
InstSeqNum nonSpecSeqNum;
|
|
|
|
bool uncached;
|
|
|
|
unsigned lqIdx;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
bool stall;
|
|
|
|
};
|
|
|
|
TimeBuffer<CommStruct> comm;
|
|
|
|
};
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
#endif // __CPU_OZONE_CPU_HH__
|