sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout

19 lines
843 B
Text
Raw Normal View History

stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
Added SPARC_SE simple timing vortex regression. --HG-- extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
2007-03-29 19:51:12 +02:00
M5 Simulator System
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
Copyright (c) 2001-2008
Added SPARC_SE simple timing vortex regression. --HG-- extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
2007-03-29 19:51:12 +02:00
The Regents of The University of Michigan
All Rights Reserved
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:06:02
M5 executing on zizzer
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Added SPARC_SE simple timing vortex regression. --HG-- extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
2007-03-29 19:51:12 +02:00
Global frequency set at 1000000000000 ticks per second
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
info: Increasing stack size by one page.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Exiting @ tick 203281649000 because target called exit()
Reference in a new issue Copy permalink