2012-08-25 20:16:45 +02:00
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/*
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* Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2009-09-11 23:19:31 +02:00
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2015-07-20 16:15:18 +02:00
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machine(MachineType:DMA, "DMA Controller")
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2014-09-01 23:55:45 +02:00
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: DMASequencer * dma_sequencer;
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Cycles request_latency := 6;
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2009-09-11 23:19:31 +02:00
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2014-09-01 23:55:47 +02:00
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MessageBuffer * responseFromDir, network="From", virtual_network="1",
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2015-08-14 07:19:45 +02:00
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vnet_type="response";
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2014-09-01 23:55:47 +02:00
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MessageBuffer * requestToDir, network="To", virtual_network="0",
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2015-08-14 07:19:45 +02:00
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vnet_type="request";
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2015-09-05 16:34:24 +02:00
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MessageBuffer * mandatoryQueue;
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2014-09-01 23:55:47 +02:00
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{
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2011-02-24 01:41:59 +01:00
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state_declaration(State, desc="DMA states", default="DMA_State_READY") {
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READY, AccessPermission:Invalid, desc="Ready to accept a new request";
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BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
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BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
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2009-09-11 23:19:31 +02:00
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}
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enumeration(Event, desc="DMA events") {
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ReadRequest, desc="A new read request";
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WriteRequest, desc="A new write request";
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Data, desc="Data from a DMA memory read";
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Ack, desc="DMA write to memory completed";
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}
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2016-10-27 04:48:37 +02:00
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Data";
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}
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structure(TBETable, external = "yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
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2015-09-16 18:59:56 +02:00
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Tick clockEdge();
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2009-09-11 23:19:31 +02:00
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2016-10-27 04:48:37 +02:00
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State getState(TBE tbe, Addr addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else {
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return State:READY;
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}
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2009-09-11 23:19:31 +02:00
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}
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2014-11-06 12:42:20 +01:00
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2016-10-27 04:48:37 +02:00
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void setState(TBE tbe, Addr addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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2009-09-11 23:19:31 +02:00
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}
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2015-08-14 19:04:51 +02:00
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AccessPermission getAccessPermission(Addr addr) {
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2011-06-08 18:58:09 +02:00
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return AccessPermission:NotPresent;
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}
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2015-08-14 19:04:51 +02:00
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void setAccessPermission(Addr addr, State state) {
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2011-06-08 18:58:09 +02:00
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}
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2015-08-14 19:04:51 +02:00
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void functionalRead(Addr addr, Packet *pkt) {
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2014-11-06 12:42:20 +01:00
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error("DMA does not support functional read.");
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}
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2015-08-14 19:04:51 +02:00
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int functionalWrite(Addr addr, Packet *pkt) {
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2014-11-06 12:42:20 +01:00
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error("DMA does not support functional write.");
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2011-07-01 02:49:26 +02:00
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}
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2014-09-01 23:55:47 +02:00
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out_port(requestToDir_out, RequestMsg, requestToDir, desc="...");
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2009-09-11 23:19:31 +02:00
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in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
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2015-09-16 18:59:56 +02:00
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if (dmaRequestQueue_in.isReady(clockEdge())) {
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2009-09-11 23:19:31 +02:00
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peek(dmaRequestQueue_in, SequencerMsg) {
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if (in_msg.Type == SequencerRequestType:LD ) {
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2016-10-27 04:48:37 +02:00
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trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
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2009-09-11 23:19:31 +02:00
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} else if (in_msg.Type == SequencerRequestType:ST) {
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2016-10-27 04:48:37 +02:00
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trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
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2009-09-11 23:19:31 +02:00
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} else {
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error("Invalid request type");
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}
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}
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}
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}
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2009-09-26 00:51:51 +02:00
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in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
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2015-09-16 18:59:56 +02:00
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if (dmaResponseQueue_in.isReady(clockEdge())) {
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2009-09-26 00:51:51 +02:00
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peek( dmaResponseQueue_in, ResponseMsg) {
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if (in_msg.Type == CoherenceResponseType:ACK) {
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2016-10-27 04:48:37 +02:00
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trigger(Event:Ack, makeLineAddress(in_msg.addr),
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TBEs[makeLineAddress(in_msg.addr)]);
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2009-09-26 00:51:51 +02:00
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} else if (in_msg.Type == CoherenceResponseType:DATA) {
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2016-10-27 04:48:37 +02:00
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trigger(Event:Data, makeLineAddress(in_msg.addr),
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TBEs[makeLineAddress(in_msg.addr)]);
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2009-09-11 23:19:31 +02:00
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} else {
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error("Invalid response type");
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}
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}
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}
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}
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action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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2014-09-01 23:55:47 +02:00
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enqueue(requestToDir_out, RequestMsg, request_latency) {
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2015-08-14 19:04:47 +02:00
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out_msg.addr := in_msg.PhysicalAddress;
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2009-09-26 00:51:51 +02:00
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out_msg.Type := CoherenceRequestType:DMA_READ;
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2009-09-11 23:19:31 +02:00
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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2014-09-01 23:55:47 +02:00
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enqueue(requestToDir_out, RequestMsg, request_latency) {
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2015-08-14 19:04:47 +02:00
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out_msg.addr := in_msg.PhysicalAddress;
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2009-09-26 00:51:51 +02:00
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out_msg.Type := CoherenceRequestType:DMA_WRITE;
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2009-09-11 23:19:31 +02:00
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
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2016-10-27 04:48:37 +02:00
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dma_sequencer.ackCallback(address);
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2009-09-11 23:19:31 +02:00
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}
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action(d_dataCallback, "d", desc="Write data to dma sequencer") {
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2016-10-27 04:48:37 +02:00
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dma_sequencer.dataCallback(tbe.DataBlk, address);
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}
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action(t_updateTBEData, "t", desc="Update TBE Data") {
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assert(is_valid(tbe));
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peek( dmaResponseQueue_in, ResponseMsg) {
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tbe.DataBlk := in_msg.DataBlk;
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2009-09-11 23:19:31 +02:00
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}
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}
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2016-10-27 04:48:37 +02:00
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action(v_allocateTBE, "v", desc="Allocate TBE entry") {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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2009-09-11 23:19:31 +02:00
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action(p_popRequestQueue, "p", desc="Pop request queue") {
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2015-09-16 18:59:56 +02:00
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dmaRequestQueue_in.dequeue(clockEdge());
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2009-09-11 23:19:31 +02:00
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}
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action(p_popResponseQueue, "\p", desc="Pop request queue") {
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2015-09-16 18:59:56 +02:00
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dmaResponseQueue_in.dequeue(clockEdge());
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2009-09-11 23:19:31 +02:00
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}
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2016-10-27 04:48:37 +02:00
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action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
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stall_and_wait(dmaRequestQueue_in, address);
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}
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action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
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wakeUpAllBuffers();
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}
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2009-09-11 23:19:31 +02:00
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transition(READY, ReadRequest, BUSY_RD) {
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2016-10-27 04:48:37 +02:00
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v_allocateTBE;
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2009-09-11 23:19:31 +02:00
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s_sendReadRequest;
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p_popRequestQueue;
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}
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transition(READY, WriteRequest, BUSY_WR) {
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2016-10-27 04:48:37 +02:00
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v_allocateTBE;
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2009-09-11 23:19:31 +02:00
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s_sendWriteRequest;
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p_popRequestQueue;
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}
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transition(BUSY_RD, Data, READY) {
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2016-10-27 04:48:37 +02:00
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t_updateTBEData;
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2009-09-11 23:19:31 +02:00
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d_dataCallback;
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2016-10-27 04:48:37 +02:00
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w_deallocateTBE;
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2009-09-11 23:19:31 +02:00
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p_popResponseQueue;
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2016-10-27 04:48:37 +02:00
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wkad_wakeUpAllDependents;
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2009-09-11 23:19:31 +02:00
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}
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transition(BUSY_WR, Ack, READY) {
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a_ackCallback;
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2016-10-27 04:48:37 +02:00
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w_deallocateTBE;
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2009-09-11 23:19:31 +02:00
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p_popResponseQueue;
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2016-10-27 04:48:37 +02:00
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wkad_wakeUpAllDependents;
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2009-09-11 23:19:31 +02:00
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}
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2016-10-27 04:48:37 +02:00
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transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
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zz_stallAndWaitRequestQueue;
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}
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2009-09-11 23:19:31 +02:00
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}
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