gem5/src/base/loader/elf_object.cc

576 lines
19 KiB
C++
Raw Normal View History

/*
* Copyright (c) 2011-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
Many files: Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 11:16:00 +02:00
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Ali Saidi
*/
#include "base/loader/elf_object.hh"
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include <cassert>
#include <string>
2011-04-15 19:44:06 +02:00
#include "base/bitfield.hh"
#include "base/loader/symtab.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/Loader.hh"
2011-04-15 19:44:06 +02:00
#include "gelf.h"
#include "sim/byteswap.hh"
ObjectFile *
ElfObject::tryFile(const std::string &fname, size_t len, uint8_t *data,
bool skip_interp_check)
{
// check that header matches library version
if (elf_version(EV_CURRENT) == EV_NONE)
panic("wrong elf version number!");
// get a pointer to elf structure
// Check that we actually have a elf file
Elf *elf = elf_memory((char*)data, len);
assert(elf);
GElf_Ehdr ehdr;
if (gelf_getehdr(elf, &ehdr) == 0) {
DPRINTFR(Loader, "Not ELF\n");
elf_end(elf);
return NULL;
}
// Detect the architecture
Arch arch = UnknownArch;
if (ehdr.e_machine == EM_SPARC64 ||
(ehdr.e_machine == EM_SPARC &&
ehdr.e_ident[EI_CLASS] == ELFCLASS64) ||
ehdr.e_machine == EM_SPARCV9) {
arch = SPARC64;
} else if (ehdr.e_machine == EM_SPARC32PLUS ||
(ehdr.e_machine == EM_SPARC &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32)) {
arch = SPARC32;
} else if (ehdr.e_machine == EM_MIPS &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = Mips;
if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
fatal("The binary you're trying to load is compiled for big "
"endian MIPS. gem5\nonly supports little endian MIPS. "
"Please recompile your binary.\n");
}
} else if (ehdr.e_machine == EM_X86_64 &&
ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = X86_64;
} else if (ehdr.e_machine == EM_386 &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = I386;
} else if (ehdr.e_machine == EM_ARM &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = bits(ehdr.e_entry, 0) ? Thumb : Arm;
} else if (ehdr.e_machine == EM_AARCH64 &&
ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = Arm64;
arch: [Patch 1/5] Added RISC-V base instruction set RV64I First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30 23:10:28 +01:00
} else if (ehdr.e_machine == EM_RISCV) {
arch = Riscv;
} else if (ehdr.e_machine == EM_PPC &&
ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = Power;
if (ehdr.e_ident[EI_DATA] != ELFDATA2MSB) {
fatal("The binary you're trying to load is compiled for "
"little endian Power.\ngem5 only supports big "
"endian Power. Please recompile your binary.\n");
}
} else if (ehdr.e_machine == EM_PPC64) {
fatal("The binary you're trying to load is compiled for 64-bit "
"Power. M5\n only supports 32-bit Power. Please "
"recompile your binary.\n");
} else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
// Since we don't know how to check for alpha right now, we'll
// just assume if it wasn't something else and it's 64 bit, that's
// what it must be.
arch = Alpha;
} else {
warn("Unknown architecture: %d\n", ehdr.e_machine);
arch = UnknownArch;
}
// Detect the operating system
OpSys op_sys;
switch (ehdr.e_ident[EI_OSABI]) {
case ELFOSABI_LINUX:
op_sys = Linux;
break;
case ELFOSABI_SOLARIS:
op_sys = Solaris;
break;
case ELFOSABI_TRU64:
op_sys = Tru64;
break;
case ELFOSABI_ARM:
op_sys = LinuxArmOABI;
break;
case ELFOSABI_FREEBSD:
op_sys = FreeBSD;
break;
default:
op_sys = UnknownOpSys;
}
// Take a look at the .note.ABI section.
// It can let us know what's what.
if (op_sys == UnknownOpSys) {
int sec_idx = 1;
// Get the first section
Elf_Scn *section = elf_getscn(elf, sec_idx);
// While there are no more sections
while (section && op_sys == UnknownOpSys) {
GElf_Shdr shdr;
gelf_getshdr(section, &shdr);
char *e_str = elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name);
if (shdr.sh_type == SHT_NOTE &&
!strcmp(".note.ABI-tag", e_str)) {
// we have found a ABI note section
// Check the 5th 32bit word for OS 0 == linux, 1 == hurd,
// 2 == solaris, 3 == freebsd
Elf_Data *raw_data = elf_rawdata(section, NULL);
assert(raw_data && raw_data->d_buf);
uint32_t raw_abi = ((uint32_t*)raw_data->d_buf)[4];
bool is_le = ehdr.e_ident[EI_DATA] == ELFDATA2LSB;
uint32_t os_abi = is_le ? htole(raw_abi) : htobe(raw_abi);
switch (os_abi) {
case 0:
op_sys = Linux;
break;
case 1:
fatal("gem5 does not support the HURD ABI.\n");
case 2:
op_sys = Solaris;
break;
case 3:
op_sys = FreeBSD;
break;
}
} // if section found
if (!strcmp(".SUNW_version", e_str) ||
!strcmp(".stab.index", e_str))
op_sys = Solaris;
section = elf_getscn(elf, ++sec_idx);
} // while sections
}
ElfObject * result = new ElfObject(fname, len, data, arch, op_sys);
// The number of headers in the file
result->_programHeaderCount = ehdr.e_phnum;
// Record the size of each entry
result->_programHeaderSize = ehdr.e_phentsize;
result->_programHeaderTable = 0;
if (result->_programHeaderCount) { // If there is a program header table
// Figure out the virtual address of the header table in the
// final memory image. We use the program headers themselves
// to translate from a file offset to the address in the image.
GElf_Phdr phdr;
uint64_t e_phoff = ehdr.e_phoff;
for (int i = 0; i < result->_programHeaderCount; i++) {
gelf_getphdr(elf, i, &phdr);
// Check if we've found the segment with the headers in it
if (phdr.p_offset <= e_phoff &&
phdr.p_offset + phdr.p_filesz > e_phoff) {
result->_programHeaderTable =
phdr.p_paddr + (e_phoff - phdr.p_offset);
break;
}
}
}
if (!skip_interp_check) {
for (int i = 0; i < ehdr.e_phnum; i++) {
GElf_Phdr phdr;
M5_VAR_USED void *check_p = gelf_getphdr(elf, i, &phdr);
assert(check_p != nullptr);
if (phdr.p_type != PT_INTERP)
continue;
char *interp_path = (char*)data + phdr.p_offset;
int fd = open(interp_path, O_RDONLY);
if (fd == -1)
fatal("Unable to open dynamic executable's interpreter.\n");
struct stat sb;
M5_VAR_USED int check_i = fstat(fd, &sb);
assert(check_i == 0);
void *mm = mmap(nullptr, sb.st_size, PROT_READ,
MAP_PRIVATE, fd, 0);
assert(mm != MAP_FAILED);
close(fd);
uint8_t *interp_image = (uint8_t*)mm;
ObjectFile *obj = tryFile(interp_path, sb.st_size,
interp_image, true);
assert(obj != nullptr);
result->interpreter = dynamic_cast<ElfObject*>(obj);
assert(result->interpreter != nullptr);
break;
}
}
elf_end(elf);
return result;
}
ElfObject::ElfObject(const std::string &_filename, size_t _len,
uint8_t *_data, Arch _arch, OpSys _op_sys)
: ObjectFile(_filename, _len, _data, _arch, _op_sys),
_programHeaderTable(0), _programHeaderSize(0), _programHeaderCount(0),
interpreter(nullptr), ldBias(0), relocate(true),
ldMin(std::numeric_limits<Addr>::max()),
ldMax(std::numeric_limits<Addr>::min())
{
// check that header matches library version
if (elf_version(EV_CURRENT) == EV_NONE)
panic("wrong elf version number!");
// get a pointer to elf structure
Elf *elf = elf_memory((char*)fileData,len);
assert(elf);
// Check that we actually have a elf file
GElf_Ehdr ehdr;
if (gelf_getehdr(elf, &ehdr) ==0) {
panic("Not ELF, shouldn't be here");
}
entry = ehdr.e_entry;
// initialize segment sizes to 0 in case they're not present
text.size = data.size = bss.size = 0;
text.baseAddr = data.baseAddr = bss.baseAddr = 0;
int sec_idx = 1;
// The first address of some important sections.
Addr text_sec_start = 0;
Addr data_sec_start = 0;
Addr bss_sec_start = 0;
// Get the first section
Elf_Scn *section = elf_getscn(elf, sec_idx);
// Find the beginning of the most interesting sections.
while (section) {
GElf_Shdr shdr;
gelf_getshdr(section, &shdr);
char *sec_name = elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name);
if (sec_name) {
if (!strcmp(".text", sec_name)) {
text_sec_start = shdr.sh_addr;
} else if (!strcmp(".data", sec_name)) {
data_sec_start = shdr.sh_addr;
} else if (!strcmp(".bss", sec_name)) {
bss_sec_start = shdr.sh_addr;
}
} else {
Elf_Error errorNum = (Elf_Error)elf_errno();
if (errorNum != ELF_E_NONE) {
const char *errorMessage = elf_errmsg(errorNum);
fatal("Error from libelf: %s.\n", errorMessage);
}
}
section = elf_getscn(elf, ++sec_idx);
}
// Go through all the segments in the program, record them, and scrape
// out information about the text, data, and bss areas needed by other
// code.
for (int i = 0; i < ehdr.e_phnum; ++i) {
GElf_Phdr phdr;
if (gelf_getphdr(elf, i, &phdr) == 0) {
panic("gelf_getphdr failed for segment %d.", i);
}
// for now we don't care about non-loadable segments
if (!(phdr.p_type & PT_LOAD))
continue;
ldMin = std::min(ldMin, phdr.p_vaddr);
ldMax = std::max(ldMax, phdr.p_vaddr + phdr.p_memsz);
// Check to see if this segment contains the bss section.
if (phdr.p_paddr <= bss_sec_start &&
phdr.p_paddr + phdr.p_memsz > bss_sec_start &&
phdr.p_memsz - phdr.p_filesz > 0) {
bss.baseAddr = phdr.p_paddr + phdr.p_filesz;
bss.size = phdr.p_memsz - phdr.p_filesz;
bss.fileImage = NULL;
}
// Check to see if this is the text or data segment
if (phdr.p_vaddr <= text_sec_start &&
phdr.p_vaddr + phdr.p_filesz > text_sec_start) {
// If this value is nonzero, we need to flip the relocate flag.
if (phdr.p_vaddr != 0)
relocate = false;
text.baseAddr = phdr.p_paddr;
text.size = phdr.p_filesz;
Simple program runs with sendAtomic! Ignoring returned latency for now. Refactored loadSections in ObjectFile hierarchy. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. base/loader/object_file.cc: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. Also explicitly load BSS now since we need to allocate the translations for it in syscall emulation. cpu/base.hh: Don't need memPort (just pass port in to ExecContext constructor). cpu/exec_context.cc: cpu/exec_context.hh: mem/port.cc: mem/translating_port.cc: mem/translating_port.hh: Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.cc: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Several more minor bug fixes. Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now. Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all). Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.hh: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Pass syscall emulation Port into constructor instead of getting it from BaseCPU. mem/physical.cc: Set packet result field. --HG-- extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02 16:31:48 +01:00
text.fileImage = fileData + phdr.p_offset;
} else if (phdr.p_vaddr <= data_sec_start &&
phdr.p_vaddr + phdr.p_filesz > data_sec_start) {
data.baseAddr = phdr.p_paddr;
data.size = phdr.p_filesz;
Simple program runs with sendAtomic! Ignoring returned latency for now. Refactored loadSections in ObjectFile hierarchy. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. base/loader/object_file.cc: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. Also explicitly load BSS now since we need to allocate the translations for it in syscall emulation. cpu/base.hh: Don't need memPort (just pass port in to ExecContext constructor). cpu/exec_context.cc: cpu/exec_context.hh: mem/port.cc: mem/translating_port.cc: mem/translating_port.hh: Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.cc: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Several more minor bug fixes. Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now. Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all). Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.hh: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Pass syscall emulation Port into constructor instead of getting it from BaseCPU. mem/physical.cc: Set packet result field. --HG-- extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02 16:31:48 +01:00
data.fileImage = fileData + phdr.p_offset;
} else {
// If it's none of the above but is loadable,
// load the filesize worth of data
Segment extra;
extra.baseAddr = phdr.p_paddr;
extra.size = phdr.p_filesz;
extra.fileImage = fileData + phdr.p_offset;
extraSegments.push_back(extra);
}
}
// should have found at least one loadable segment
warn_if(text.size == 0,
"Empty .text segment in '%s'. ELF file corrupted?\n",
filename);
DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n",
text.baseAddr, text.size, data.baseAddr, data.size,
bss.baseAddr, bss.size);
elf_end(elf);
// We will actually read the sections when we need to load them
}
bool
ElfObject::loadSomeSymbols(SymbolTable *symtab, int binding, Addr mask,
Addr base, Addr offset)
{
if (!symtab)
return false;
// check that header matches library version
if (elf_version(EV_CURRENT) == EV_NONE)
panic("wrong elf version number!");
// get a pointer to elf structure
Elf *elf = elf_memory((char*)fileData,len);
assert(elf != NULL);
// Get the first section
int sec_idx = 1; // there is a 0 but it is nothing, go figure
Elf_Scn *section = elf_getscn(elf, sec_idx);
// While there are no more sections
bool found = false;
while (section != NULL) {
GElf_Shdr shdr;
gelf_getshdr(section, &shdr);
if (shdr.sh_type == SHT_SYMTAB) {
found = true;
Elf_Data *data = elf_getdata(section, NULL);
int count = shdr.sh_size / shdr.sh_entsize;
DPRINTF(Loader, "Found Symbol Table, %d symbols present\n", count);
// loop through all the symbols, only loading global ones
for (int i = 0; i < count; ++i) {
GElf_Sym sym;
gelf_getsym(data, i, &sym);
if (GELF_ST_BIND(sym.st_info) == binding) {
char *sym_name = elf_strptr(elf, shdr.sh_link, sym.st_name);
if (sym_name && sym_name[0] != '$') {
Addr value = sym.st_value - base + offset;
if (symtab->insert(value & mask, sym_name)) {
DPRINTF(Loader, "Symbol: %-40s value %#x\n",
sym_name, value);
}
}
}
}
}
++sec_idx;
section = elf_getscn(elf, sec_idx);
}
elf_end(elf);
return found;
}
bool
ElfObject::loadAllSymbols(SymbolTable *symtab, Addr base, Addr offset,
Addr addr_mask)
{
return (loadGlobalSymbols(symtab, base, offset, addr_mask) &&
loadLocalSymbols(symtab, base, offset, addr_mask) &&
loadWeakSymbols(symtab, base, offset, addr_mask));
}
bool
ElfObject::loadGlobalSymbols(SymbolTable *symtab, Addr base, Addr offset,
Addr addr_mask)
{
if (interpreter) {
interpreter->loadSomeSymbols(symtab, STB_GLOBAL, addr_mask,
base, offset);
}
return loadSomeSymbols(symtab, STB_GLOBAL, addr_mask, base, offset);
}
bool
ElfObject::loadLocalSymbols(SymbolTable *symtab, Addr base, Addr offset,
Addr addr_mask)
{
if (interpreter) {
interpreter->loadSomeSymbols(symtab, STB_LOCAL, addr_mask,
base, offset);
}
return loadSomeSymbols(symtab, STB_LOCAL, addr_mask, base, offset);
}
bool
ElfObject::loadWeakSymbols(SymbolTable *symtab, Addr base, Addr offset,
Addr addr_mask)
{
if (interpreter) {
interpreter->loadSomeSymbols(symtab, STB_WEAK, addr_mask,
base, offset);
}
return loadSomeSymbols(symtab, STB_WEAK, addr_mask, base, offset);
}
bool
ElfObject::loadSections(PortProxy& mem_proxy, Addr addr_mask, Addr offset)
{
if (!ObjectFile::loadSections(mem_proxy, addr_mask, offset))
return false;
for (auto seg : extraSegments) {
if (!loadSection(&seg, mem_proxy, addr_mask, offset)) {
return false;
}
}
if (interpreter)
interpreter->loadSections(mem_proxy, addr_mask, offset);
return true;
}
void
ElfObject::getSections()
{
assert(!sectionNames.size());
// check that header matches library version
if (elf_version(EV_CURRENT) == EV_NONE)
panic("wrong elf version number!");
// get a pointer to elf structure
Elf *elf = elf_memory((char*)fileData,len);
assert(elf != NULL);
// Check that we actually have a elf file
GElf_Ehdr ehdr;
if (gelf_getehdr(elf, &ehdr) ==0) {
panic("Not ELF, shouldn't be here");
}
// Get the first section
int sec_idx = 1; // there is a 0 but it is nothing, go figure
Elf_Scn *section = elf_getscn(elf, sec_idx);
// While there are no more sections
while (section) {
GElf_Shdr shdr;
gelf_getshdr(section, &shdr);
sectionNames.insert(elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name));
section = elf_getscn(elf, ++sec_idx);
} // while sections
}
bool
ElfObject::sectionExists(std::string sec)
{
if (!sectionNames.size())
getSections();
return sectionNames.find(sec) != sectionNames.end();
}
void
ElfObject::updateBias(Addr bias_addr)
{
// Record the bias.
ldBias = bias_addr;
// Patch the entry point with bias_addr.
entry += bias_addr;
// Patch segments with the bias_addr.
text.baseAddr += bias_addr;
data.baseAddr += bias_addr;
bss.baseAddr += bias_addr;
for (auto &segment : extraSegments)
segment.baseAddr += bias_addr;
}