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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 51.320469 # Number of seconds simulated
sim_ticks 51320468905000 # Number of ticks simulated
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
host_inst_rate 81731 # Simulator instruction rate (inst/s)
host_op_rate 96032 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4902851121 # Simulator tick rate (ticks/s)
host_mem_usage 723872 # Number of bytes of host memory used
host_seconds 10467.47 # Real time elapsed on the host
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_insts 855512158 # Number of instructions simulated
sim_ops 1005211605 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory
system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory
system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 784654 # Number of read requests accepted
system.physmem.writeReqs 1688539 # Number of write requests accepted
system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue
system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 46664 # Per bank write bursts
system.physmem.perBankRdBursts::1 51485 # Per bank write bursts
system.physmem.perBankRdBursts::2 48018 # Per bank write bursts
system.physmem.perBankRdBursts::3 46409 # Per bank write bursts
system.physmem.perBankRdBursts::4 44064 # Per bank write bursts
system.physmem.perBankRdBursts::5 51949 # Per bank write bursts
system.physmem.perBankRdBursts::6 45895 # Per bank write bursts
system.physmem.perBankRdBursts::7 48923 # Per bank write bursts
system.physmem.perBankRdBursts::8 45299 # Per bank write bursts
system.physmem.perBankRdBursts::9 70789 # Per bank write bursts
system.physmem.perBankRdBursts::10 48156 # Per bank write bursts
system.physmem.perBankRdBursts::11 46739 # Per bank write bursts
system.physmem.perBankRdBursts::12 48771 # Per bank write bursts
system.physmem.perBankRdBursts::13 48997 # Per bank write bursts
system.physmem.perBankRdBursts::14 45133 # Per bank write bursts
system.physmem.perBankRdBursts::15 46835 # Per bank write bursts
system.physmem.perBankWrBursts::0 99610 # Per bank write bursts
system.physmem.perBankWrBursts::1 104326 # Per bank write bursts
system.physmem.perBankWrBursts::2 103481 # Per bank write bursts
system.physmem.perBankWrBursts::3 102430 # Per bank write bursts
system.physmem.perBankWrBursts::4 101747 # Per bank write bursts
system.physmem.perBankWrBursts::5 104971 # Per bank write bursts
system.physmem.perBankWrBursts::6 100056 # Per bank write bursts
system.physmem.perBankWrBursts::7 103888 # Per bank write bursts
system.physmem.perBankWrBursts::8 99840 # Per bank write bursts
system.physmem.perBankWrBursts::9 106110 # Per bank write bursts
system.physmem.perBankWrBursts::10 102643 # Per bank write bursts
system.physmem.perBankWrBursts::11 100858 # Per bank write bursts
system.physmem.perBankWrBursts::12 103355 # Per bank write bursts
system.physmem.perBankWrBursts::13 103593 # Per bank write bursts
system.physmem.perBankWrBursts::14 100350 # Per bank write bursts
system.physmem.perBankWrBursts::15 101960 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.numWrRetry 560 # Number of times write queue was full causing retry
system.physmem.totGap 51320467654000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::6 763369 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writePktSize::6 1685966 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads
system.physmem.totQLat 15388206863 # Total ticks spent queuing
system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing
system.physmem.readRowHits 598254 # Number of row buffer hits during reads
system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes
system.physmem.avgGap 20750692.59 # Average gap between requests
system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.470318 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.479291 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.lookups 226088242 # Number of BP lookups
system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups
system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.walker.walks 200795 # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong 200795 # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 200795 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 200795 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 200795 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples 1638530500 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 1638530500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 1638530500 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walkPageSizes::4K 155523 90.97% 90.97% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::2M 15432 9.03% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 170955 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200795 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200795 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170955 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170955 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 371750 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.read_hits 160924630 # DTB read hits
system.cpu.checker.dtb.read_misses 149513 # DTB read misses
system.cpu.checker.dtb.write_hits 145982592 # DTB write hits
system.cpu.checker.dtb.write_misses 51282 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 72580 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.prefetch_faults 7050 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.perms_faults 19166 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 161074143 # DTB read accesses
system.cpu.checker.dtb.write_accesses 146033874 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.dtb.hits 306907222 # DTB hits
system.cpu.checker.dtb.misses 200795 # DTB misses
system.cpu.checker.dtb.accesses 307108017 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.itb.walker.walks 120591 # Table walker walks requested
system.cpu.checker.itb.walker.walksLong 120591 # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 120591 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 120591 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 120591 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 1637932000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 1637932000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 1637932000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 108617 98.83% 98.83% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M 1291 1.17% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 109908 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120591 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120591 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109908 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109908 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 230499 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits 855922330 # ITB inst hits
system.cpu.checker.itb.inst_misses 120591 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 52096 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.checker.itb.inst_accesses 856042921 # ITB inst accesses
system.cpu.checker.itb.hits 855922330 # DTB hits
system.cpu.checker.itb.misses 120591 # DTB misses
system.cpu.checker.itb.accesses 856042921 # DTB accesses
system.cpu.checker.numCycles 1005785493 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walks 945525 # Table walker walks requested
system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.read_hits 170900022 # DTB read hits
system.cpu.dtb.read_misses 675244 # DTB read misses
system.cpu.dtb.write_hits 148749524 # DTB write hits
system.cpu.dtb.write_misses 270281 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 171575266 # DTB read accesses
system.cpu.dtb.write_accesses 149019805 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.hits 319649546 # DTB hits
system.cpu.dtb.misses 945525 # DTB misses
system.cpu.dtb.accesses 320595071 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walks 161869 # Table walker walks requested
system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 359459512 # ITB inst hits
system.cpu.itb.inst_misses 161869 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.inst_accesses 359621381 # ITB inst accesses
system.cpu.itb.hits 359459512 # DTB hits
system.cpu.itb.misses 161869 # DTB misses
system.cpu.itb.accesses 359621381 # DTB accesses
system.cpu.numCycles 1580751099 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed
system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.iqSquashedInstsExamined 60716319 # Number of squashed instructions iterated over during squash; mainly for profiling
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued
system.cpu.iq.rate 0.666896 # Inst issue rate
system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.int_inst_queue_writes 1125839347 # Number of integer instruction queue writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.fp_inst_queue_writes 946702 # Number of floating instruction queue writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_nop 222943 # number of nop insts executed
system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed
system.cpu.iew.exec_branches 197926826 # Number of branches executed
system.cpu.iew.exec_stores 148745526 # Number of stores executed
system.cpu.iew.exec_rate 0.659804 # Inst execution rate
system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back
system.cpu.iew.wb_producers 441278048 # num instructions producing a value
system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle
system.cpu.commit.committedInsts 855512158 # Number of instructions committed
system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.refs 307009160 # Number of memory references committed
system.cpu.commit.loads 161022390 # Number of loads committed
system.cpu.commit.membars 6998413 # Number of memory barriers committed
system.cpu.commit.branches 190975004 # Number of branches committed
system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions.
system.cpu.commit.int_insts 923410198 # Number of committed integer instructions.
system.cpu.commit.function_calls 25456304 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 855512158 # Number of Instructions Simulated
system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads
system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads
system.cpu.int_regfile_writes 737118920 # number of integer regfile writes
system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads
system.cpu.fp_regfile_writes 784484 # number of floating regfile writes
system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads
system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes
system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads
system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9794555 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits
system.cpu.dcache.overall_hits::total 278057664 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses
system.cpu.dcache.overall_misses::total 22142972 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks
system.cpu.dcache.writebacks::total 7577660 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements 15070815 # number of replacements
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses
system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits
system.cpu.icache.overall_hits::total 343233622 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses
system.cpu.icache.overall_misses::total 15815747 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits
system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses
system.cpu.l2cache.overall_misses::total 758194 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks
system.cpu.l2cache.writebacks::total 977263 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::ReadReq 40283 # Transaction distribution
system.iobus.trans_dist::ReadResp 40283 # Transaction distribution
system.iobus.trans_dist::WriteReq 136558 # Transaction distribution
system.iobus.trans_dist::WriteResp 29894 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.replacements 115456 # number of replacements
system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.tag_accesses 1039632 # Number of tag accesses
system.iocache.tags.data_accesses 1039632 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses
system.iocache.demand_misses::total 8851 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_misses::realview.ide 8811 # number of overall misses
system.iocache.overall_misses::total 8851 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 408284 # Transaction distribution
system.membus.trans_dist::ReadResp 408284 # Transaction distribution
system.membus.trans_dist::WriteReq 33682 # Transaction distribution
system.membus.trans_dist::WriteResp 33682 # Transaction distribution
system.membus.trans_dist::Writeback 1083893 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution
system.membus.trans_dist::ReadExReq 413056 # Transaction distribution
system.membus.trans_dist::ReadExResp 413056 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3023 # Total snoops (count)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::samples 2576774 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::total 2576774 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink