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gem5/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt

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SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
---------- Begin Simulation Statistics ----------
sim_seconds 0.100000 # Number of seconds simulated
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
host_tick_rate 20181472495 # Simulator tick rate (ticks/s)
host_mem_usage 192916 # Number of bytes of host memory used
host_seconds 4.96 # Real time elapsed on the host
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readReqs 3333300 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 217600 # Per bank write bursts
system.physmem.perBankRdBursts::1 217600 # Per bank write bursts
system.physmem.perBankRdBursts::2 217600 # Per bank write bursts
system.physmem.perBankRdBursts::3 217600 # Per bank write bursts
system.physmem.perBankRdBursts::4 210100 # Per bank write bursts
system.physmem.perBankRdBursts::5 204800 # Per bank write bursts
system.physmem.perBankRdBursts::6 204800 # Per bank write bursts
system.physmem.perBankRdBursts::7 204800 # Per bank write bursts
system.physmem.perBankRdBursts::8 204800 # Per bank write bursts
system.physmem.perBankRdBursts::9 204800 # Per bank write bursts
system.physmem.perBankRdBursts::10 204800 # Per bank write bursts
system.physmem.perBankRdBursts::11 204800 # Per bank write bursts
system.physmem.perBankRdBursts::12 204800 # Per bank write bursts
system.physmem.perBankRdBursts::13 204800 # Per bank write bursts
system.physmem.perBankRdBursts::14 204800 # Per bank write bursts
system.physmem.perBankRdBursts::15 204800 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.totGap 99999960000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 3333300 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation
system.physmem.totQLat 27766345550 # Total ticks spent queuing
system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers
system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks
system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 16.67 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 3294382 # Number of row buffer hits during reads
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgGap 30000.29 # Average gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.throughput 2133311360 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.data_through_bus 213331136 # Total data (bytes)
system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::0 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::1 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::2 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::3 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::4 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::5 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::6 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::7 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::8 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::9 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::10 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::11 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::12 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::13 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::14 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::15 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::16 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::17 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::18 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s)
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09 100 100.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s)
system.monitor.totalReadBytes 213331136 # Number of bytes read
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::stdev 0 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::0 100 100.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::1 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::2 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::3 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::4 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::5 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::6 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::7 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::8 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::9 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::10 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::11 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::12 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::13 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::14 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::15 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::16 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::17 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::18 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::19 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
system.monitor.totalWrittenBytes 0 # Number of bytes written
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency
system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency
system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency
system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency
system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency
system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency
system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency
system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency
system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency
system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency
system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency
system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency
system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency
system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::458752-491519 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::491520-524287 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readLatencyHist::total 3333299 # Read request-response latency
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.writeLatencyHist::samples 0 # Write request-response latency
system.monitor.writeLatencyHist::mean nan # Write request-response latency
system.monitor.writeLatencyHist::gmean nan # Write request-response latency
system.monitor.writeLatencyHist::stdev nan # Write request-response latency
system.monitor.writeLatencyHist::0 0 # Write request-response latency
system.monitor.writeLatencyHist::1 0 # Write request-response latency
system.monitor.writeLatencyHist::2 0 # Write request-response latency
system.monitor.writeLatencyHist::3 0 # Write request-response latency
system.monitor.writeLatencyHist::4 0 # Write request-response latency
system.monitor.writeLatencyHist::5 0 # Write request-response latency
system.monitor.writeLatencyHist::6 0 # Write request-response latency
system.monitor.writeLatencyHist::7 0 # Write request-response latency
system.monitor.writeLatencyHist::8 0 # Write request-response latency
system.monitor.writeLatencyHist::9 0 # Write request-response latency
system.monitor.writeLatencyHist::10 0 # Write request-response latency
system.monitor.writeLatencyHist::11 0 # Write request-response latency
system.monitor.writeLatencyHist::12 0 # Write request-response latency
system.monitor.writeLatencyHist::13 0 # Write request-response latency
system.monitor.writeLatencyHist::14 0 # Write request-response latency
system.monitor.writeLatencyHist::15 0 # Write request-response latency
system.monitor.writeLatencyHist::16 0 # Write request-response latency
system.monitor.writeLatencyHist::17 0 # Write request-response latency
system.monitor.writeLatencyHist::18 0 # Write request-response latency
system.monitor.writeLatencyHist::19 0 # Write request-response latency
system.monitor.writeLatencyHist::total 0 # Write request-response latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReadRead::samples 3333299 # Read-to-read inter transaction time
system.monitor.ittReadRead::mean 30000.297003 # Read-to-read inter transaction time
system.monitor.ittReadRead::stdev 54.497186 # Read-to-read inter transaction time
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReadRead::5001-10000 0 0.00% 0.00% # Read-to-read inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReadRead::25001-30000 3333200 100.00% 100.00% # Read-to-read inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReadRead::30001-35000 0 0.00% 100.00% # Read-to-read inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReadRead::35001-40000 99 0.00% 100.00% # Read-to-read inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReadRead::40001-45000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::45001-50000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::50001-55000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::55001-60000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::60001-65000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::65001-70000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::70001-75000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::75001-80000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::80001-85000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::85001-90000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::90001-95000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::95001-100000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReadRead::min_value 30000 # Read-to-read inter transaction time
system.monitor.ittReadRead::max_value 40000 # Read-to-read inter transaction time
system.monitor.ittReadRead::total 3333299 # Read-to-read inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time
system.monitor.ittWriteWrite::underflows 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::1-5000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::5001-10000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::10001-15000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::15001-20000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::20001-25000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::25001-30000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::30001-35000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::35001-40000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::40001-45000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::45001-50000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::50001-55000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::55001-60000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::60001-65000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::65001-70000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::70001-75000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::75001-80000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::80001-85000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::85001-90000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::90001-95000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::95001-100000 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::overflows 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReqReq::samples 3333299 # Request-to-request inter transaction time
system.monitor.ittReqReq::mean 30000.297003 # Request-to-request inter transaction time
system.monitor.ittReqReq::stdev 54.497186 # Request-to-request inter transaction time
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReqReq::25001-30000 3333200 100.00% 100.00% # Request-to-request inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::55001-60000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.ittReqReq::min_value 30000 # Request-to-request inter transaction time
system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time
system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions
system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions
system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::12 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::13 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::14 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::15 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::16 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::17 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Outstanding read transactions
system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions
system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.outstandingWritesHist::mean 0 # Outstanding write transactions
system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions
system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions
system.monitor.outstandingWritesHist::0 100 100.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::1 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period
system.monitor.readTransHist::gmean 33333.000000 # Histogram of read transactions per sample period
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period
system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07 19:05:36 +01:00
system.monitor.writeTransHist::mean 0 # Histogram of read transactions per sample period
system.monitor.writeTransHist::gmean 0 # Histogram of read transactions per sample period
system.monitor.writeTransHist::stdev 0 # Histogram of read transactions per sample period
system.monitor.writeTransHist::0 100 100.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::1 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.numPackets 3333300 # Number of packets generated
system.cpu.numRetries 0 # Number of retries
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
SimpleDRAM: A basic SimpleDRAM regression --HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 17:48:14 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink