2006-09-01 23:59:36 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
|
|
|
global.BPredUnit.BTBHits 542 # Number of BTB hits
|
2006-10-07 18:58:37 +02:00
|
|
|
global.BPredUnit.BTBLookups 1936 # Number of BTB lookups
|
2006-09-01 23:59:36 +02:00
|
|
|
global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
|
2006-10-07 18:58:37 +02:00
|
|
|
global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 2254 # Number of BP lookups
|
2006-09-01 23:59:36 +02:00
|
|
|
global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
|
2006-10-09 03:08:27 +02:00
|
|
|
host_inst_rate 46995 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 160420 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.12 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 57256 # Simulator tick rate (ticks/s)
|
2006-09-01 23:59:36 +02:00
|
|
|
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
|
2006-10-07 18:58:37 +02:00
|
|
|
memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit.
|
2006-09-01 23:59:36 +02:00
|
|
|
memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 5623 # Number of instructions simulated
|
|
|
|
|
sim_seconds 0.000000 # Number of seconds simulated
|
2006-10-07 18:58:37 +02:00
|
|
|
sim_ticks 6868 # Number of ticks simulated
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:branches 862 # Number of branches committed
|
|
|
|
|
system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 6115
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2006-10-07 18:58:37 +02:00
|
|
|
0 3908 6390.84%
|
|
|
|
|
1 1063 1738.35%
|
|
|
|
|
2 389 636.14%
|
|
|
|
|
3 210 343.42%
|
|
|
|
|
4 152 248.57%
|
|
|
|
|
5 94 153.72%
|
|
|
|
|
6 76 124.28%
|
|
|
|
|
7 149 243.66%
|
|
|
|
|
8 74 121.01%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.commit.COM:count 5640 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 979 # Number of loads committed
|
|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.COM:refs 1791 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts 5623 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_hits 2040 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 308 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 6869
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2006-10-07 18:58:37 +02:00
|
|
|
0 4548 6621.05%
|
|
|
|
|
1 174 253.31%
|
|
|
|
|
2 186 270.78%
|
|
|
|
|
3 157 228.56%
|
|
|
|
|
4 211 307.18%
|
|
|
|
|
5 153 222.74%
|
|
|
|
|
6 171 248.94%
|
|
|
|
|
7 105 152.86%
|
|
|
|
|
8 1164 1694.57%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_hits 1255 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 327 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.iew.EXEC:branches 1206 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 37 # number of nop insts executed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.iew.EXEC:stores 985 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.WB:consumers 5409 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 7670 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.WB:producers 4025 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
|
|
|
(null) 2 0.02% # Type of FU issued
|
2006-10-07 18:58:37 +02:00
|
|
|
IntAlu 5573 66.67% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
IntMult 1 0.01% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2006-10-07 18:58:37 +02:00
|
|
|
MemRead 1757 21.02% # Type of FU issued
|
|
|
|
|
MemWrite 1024 12.25% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst)
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 1 0.87% # attempts to use FU when none available
|
|
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
MemRead 76 66.09% # attempts to use FU when none available
|
|
|
|
|
MemWrite 38 33.04% # attempts to use FU when none available
|
|
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 6869
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2006-10-07 18:58:37 +02:00
|
|
|
0 3761 5475.32%
|
|
|
|
|
1 891 1297.13%
|
|
|
|
|
2 720 1048.19%
|
|
|
|
|
3 617 898.24%
|
|
|
|
|
4 445 647.84%
|
|
|
|
|
5 278 404.72%
|
|
|
|
|
6 104 151.40%
|
|
|
|
|
7 41 59.69%
|
|
|
|
|
8 12 17.47%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.overall_misses 492 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use
|
2006-10-09 03:08:27 +02:00
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.numCycles 6869 # number of cpu cycles simulated
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
