2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2012-07-09 18:35:41 +02:00
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sim_seconds 0.028553 # Number of seconds simulated
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sim_ticks 28553466500 # Number of ticks simulated
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final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-07-09 18:35:41 +02:00
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host_inst_rate 181848 # Simulator instruction rate (inst/s)
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host_op_rate 183154 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 57311644 # Simulator tick rate (ticks/s)
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host_mem_usage 367800 # Number of bytes of host memory used
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host_seconds 498.21 # Real time elapsed on the host
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sim_insts 90599368 # Number of instructions simulated
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sim_ops 91249921 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
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system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s)
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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2012-07-09 18:35:41 +02:00
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system.cpu.numCycles 57106934 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-07-09 18:35:41 +02:00
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system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-07-09 18:35:41 +02:00
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system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked
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2012-06-29 17:19:03 +02:00
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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2012-07-09 18:35:41 +02:00
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system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2012-07-09 18:35:41 +02:00
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system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-07-09 18:35:41 +02:00
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system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2012-07-09 18:35:41 +02:00
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system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2012-07-09 18:35:41 +02:00
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system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-07-09 18:35:41 +02:00
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system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
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|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.850751 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.exec_nop 36382 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 21352915 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 5076392 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.832232 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 61949538 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 90611977 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 91262530 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 706178 1.33% 88.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 261507 0.49% 90.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 5166197 9.75% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 52991397 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committedInsts 90611977 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.refs 27322638 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 22575880 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.branches 18722474 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.int_insts 72533330 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.bw_lim_events 5166197 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.rob.rob_reads 167023568 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 242480145 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 16985 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 64617 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 90599368 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.630324 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.630324 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.586486 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.586486 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 497500268 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 120842597 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 229 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 593 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 183620284 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 11612 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 3 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 638.455928 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 14143171 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 734 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 19268.625341 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 638.455928 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.311746 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.311746 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 14143171 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 14143171 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 14143171 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 14143171 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 14143171 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 14143171 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 967 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35020500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 35020500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 35020500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 35020500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 35020500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 35020500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 14144138 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 14144138 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 14144138 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 14144138 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 14144138 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 14144138 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000068 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000068 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000068 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 36215.615305 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 36215.615305 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 233 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 233 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 233 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 233 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 233 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26444000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 26444000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26444000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 26444000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26444000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 26444000 # number of overall MSHR miss cycles
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.replacements 943512 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3689.791275 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 28381642 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 29.950826 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 8154700000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 3689.791275 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.900828 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.900828 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23801988 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 23801988 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4567984 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 4567984 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5869 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5869 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 28369972 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 28369972 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 28369972 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 28369972 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1060525 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1060525 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 166997 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 166997 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1227522 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1227522 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1227522 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1227522 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 21965060500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 21965060500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6217004264 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 6217004264 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 153500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 153500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 28182064764 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 28182064764 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 28182064764 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 28182064764 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24862513 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 24862513 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5877 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5877 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 29597494 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 29597494 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 29597494 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 29597494 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042656 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.042656 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035269 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.035269 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001361 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001361 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 22958.500755 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 22958.500755 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 78852438 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 9147 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8620.579206 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 942869 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 942869 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148009 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 148009 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131905 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 131905 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 279914 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 279914 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 279914 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 279914 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912516 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 912516 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35092 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 35092 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 947608 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 947608 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 947608 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 947608 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16755802500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16755802500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751499399 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751499399 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18507301899 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 18507301899 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18507301899 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18507301899 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036702 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036702 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007411 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007411 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032016 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032016 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 10958.956435 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1839863 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15497 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 118.723818 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 10102.128367 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 622.173685 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 234.654384 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.308292 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.018987 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.007161 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.334441 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 912088 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 912112 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942869 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 942869 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 20704 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 20704 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 932792 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 932816 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 932792 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 932816 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 710 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14535 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 14535 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 710 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.demand_misses::total 15526 # number of demand (read+write) misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 710 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.overall_misses::total 15526 # number of overall misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25363000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10310000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 35673000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499681500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 499681500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 25363000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 509991500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 535354500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 25363000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 509991500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 535354500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 734 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 912369 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 913103 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942869 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 942869 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 35239 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 35239 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 734 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 734 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967302 # miss rate for ReadReq accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001085 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412469 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.412469 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967302 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015635 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016372 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967302 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015635 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016372 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35722.535211 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36690.391459 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35996.972755 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34377.812178 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34377.812178 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34481.160634 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34481.160634 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 708 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 708 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 708 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23086000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9134000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32220000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453439000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453439000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23086000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462573000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 485659000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23086000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462573000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 485659000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for ReadReq accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412469 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412469 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
