gem5/src/arch/sparc/faults.cc

728 lines
22 KiB
C++
Raw Normal View History

Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Kevin Lim
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
*/
#include <algorithm>
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/process.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
#include "base/trace.hh"
#include "sim/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/full_system.hh"
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
using namespace std;
namespace SparcISA
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
{
template<> SparcFaultBase::FaultVals
SparcFault<PowerOnReset>::vals =
{"power_on_reset", 0x001, 0, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<WatchDogReset>::vals =
{"watch_dog_reset", 0x002, 120, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<ExternallyInitiatedReset>::vals =
{"externally_initiated_reset", 0x003, 110, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<SoftwareInitiatedReset>::vals =
{"software_initiated_reset", 0x004, 130, {SH, SH, H}};
template<> SparcFaultBase::FaultVals
SparcFault<REDStateException>::vals =
{"RED_state_exception", 0x005, 1, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<StoreError>::vals =
{"store_error", 0x007, 201, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessException>::vals =
{"instruction_access_exception", 0x008, 300, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessMMUMiss>::vals =
{"inst_mmu", 0x009, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessError>::vals =
{"instruction_access_error", 0x00A, 400, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<IllegalInstruction>::vals =
{"illegal_instruction", 0x010, 620, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PrivilegedOpcode>::vals =
{"privileged_opcode", 0x011, 700, {P, SH, SH}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<UnimplementedLDD>::vals =
{"unimp_ldd", 0x012, 6, {H, H, H}};*/
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<UnimplementedSTD>::vals =
{"unimp_std", 0x013, 6, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<FpDisabled>::vals =
{"fp_disabled", 0x020, 800, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FpExceptionIEEE754>::vals =
{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FpExceptionOther>::vals =
{"fp_exception_other", 0x022, 1110, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TagOverflow>::vals =
{"tag_overflow", 0x023, 1400, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<CleanWindow>::vals =
{"clean_window", 0x024, 1010, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DivisionByZero>::vals =
{"division_by_zero", 0x028, 1500, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InternalProcessorError>::vals =
{"internal_processor_error", 0x029, 4, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionInvalidTSBEntry>::vals =
{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DataInvalidTSBEntry>::vals =
{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessException>::vals =
{"data_access_exception", 0x030, 1201, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<DataAccessMMUMiss>::vals =
{"data_mmu", 0x031, 12, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessError>::vals =
{"data_access_error", 0x032, 1210, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessProtection>::vals =
{"data_access_protection", 0x033, 1207, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<MemAddressNotAligned>::vals =
{"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<LDDFMemAddressNotAligned>::vals =
{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<STDFMemAddressNotAligned>::vals =
{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PrivilegedAction>::vals =
{"privileged_action", 0x037, 1110, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<LDQFMemAddressNotAligned>::vals =
{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<STQFMemAddressNotAligned>::vals =
{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionRealTranslationMiss>::vals =
{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DataRealTranslationMiss>::vals =
{"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<AsyncDataError>::vals =
{"async_data", 0x040, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<InterruptLevelN>::vals =
{"interrupt_level_n", 0x040, 0, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<HstickMatch>::vals =
{"hstick_match", 0x05E, 1601, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TrapLevelZero>::vals =
{"trap_level_zero", 0x05F, 202, {H, H, SH}};
Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 23:22:47 +01:00
template<> SparcFaultBase::FaultVals
SparcFault<InterruptVector>::vals =
{"interrupt_vector", 0x060, 2630, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PAWatchpoint>::vals =
{"PA_watchpoint", 0x061, 1209, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<VAWatchpoint>::vals =
{"VA_watchpoint", 0x062, 1120, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<FastInstructionAccessMMUMiss>::vals =
{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<FastDataAccessMMUMiss>::vals =
{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FastDataAccessProtection>::vals =
{"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionBreakpoint>::vals =
{"instruction_break", 0x076, 610, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<CpuMondo>::vals =
{"cpu_mondo", 0x07C, 1608, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DevMondo>::vals =
{"dev_mondo", 0x07D, 1611, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<ResumableError>::vals =
{"resume_error", 0x07E, 3330, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<SpillNNormal>::vals =
{"spill_n_normal", 0x080, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<SpillNOther>::vals =
{"spill_n_other", 0x0A0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FillNNormal>::vals =
{"fill_n_normal", 0x0C0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FillNOther>::vals =
{"fill_n_other", 0x0E0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TrapInstruction>::vals =
{"trap_instruction", 0x100, 1602, {P, P, H}};
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
/**
* This causes the thread context to enter RED state. This causes the side
* effects which go with entering RED state because of a trap.
*/
void
enterREDState(ThreadContext *tc)
{
//@todo Disable the mmu?
//@todo Disable watchpoints?
HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
hpstate.red = 1;
hpstate.hpriv = 1;
tc->setMiscReg(MISCREG_HPSTATE, hpstate);
// PSTATE.priv is set to 1 here. The manual says it should be 0, but
// Legion sets it to 1.
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
pstate.priv = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
}
/**
* This sets everything up for a RED state trap except for actually jumping to
* the handler.
*/
void
doREDFault(ThreadContext *tc, TrapType tt)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
PCState pc = tc->pcState();
TL++;
Addr pcMask = pstate.am ? mask(32) : mask(64);
// set TSTATE.gl to gl
replaceBits(TSTATE, 42, 40, GL);
// set TSTATE.ccr to ccr
replaceBits(TSTATE, 39, 32, CCR);
// set TSTATE.asi to asi
replaceBits(TSTATE, 31, 24, ASI);
// set TSTATE.pstate to pstate
replaceBits(TSTATE, 20, 8, pstate);
// set TSTATE.cwp to cwp
replaceBits(TSTATE, 4, 0, CWP);
// Write back TSTATE
tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
// set TPC to PC
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
// set TNPC to NPC
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
// set HTSTATE.hpstate to hpstate
tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
// TT = trap type;
tc->setMiscRegNoEffect(MISCREG_TT, tt);
// Update GL
tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
bool priv = pstate.priv; // just save the priv bit
pstate = 0;
pstate.priv = priv;
pstate.pef = 1;
tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
hpstate.red = 1;
hpstate.hpriv = 1;
hpstate.ibe = 0;
hpstate.tlz = 0;
tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
bool changedCWP = true;
if (tt == 0x24)
CWP++;
else if (0x80 <= tt && tt <= 0xbf)
CWP += (CANSAVE + 2);
else if (0xc0 <= tt && tt <= 0xff)
CWP--;
else
changedCWP = false;
if (changedCWP) {
CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP);
}
}
/**
* This sets everything up for a normal trap except for actually jumping to
* the handler.
*/
void
doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
PCState pc = tc->pcState();
// Increment the trap level
TL++;
tc->setMiscRegNoEffect(MISCREG_TL, TL);
Addr pcMask = pstate.am ? mask(32) : mask(64);
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
// Save off state
// set TSTATE.gl to gl
replaceBits(TSTATE, 42, 40, GL);
// set TSTATE.ccr to ccr
replaceBits(TSTATE, 39, 32, CCR);
// set TSTATE.asi to asi
replaceBits(TSTATE, 31, 24, ASI);
// set TSTATE.pstate to pstate
replaceBits(TSTATE, 20, 8, pstate);
// set TSTATE.cwp to cwp
replaceBits(TSTATE, 4, 0, CWP);
// Write back TSTATE
tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
// set TPC to PC
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
// set TNPC to NPC
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
// set HTSTATE.hpstate to hpstate
tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
// TT = trap type;
tc->setMiscRegNoEffect(MISCREG_TT, tt);
// Update the global register level
if (!gotoHpriv)
tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
else
tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
// pstate.mm is unchanged
pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
pstate.am = 0;
pstate.ie = 0;
// pstate.tle is unchanged
// pstate.tct = 0
if (gotoHpriv) {
pstate.cle = 0;
// The manual says PSTATE.priv should be 0, but Legion leaves it alone
hpstate.red = 0;
hpstate.hpriv = 1;
hpstate.ibe = 0;
// hpstate.tlz is unchanged
tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
} else { // we are going to priv
pstate.priv = 1;
pstate.cle = pstate.tle;
}
tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
bool changedCWP = true;
if (tt == 0x24)
CWP++;
else if (0x80 <= tt && tt <= 0xbf)
CWP += (CANSAVE + 2);
else if (0xc0 <= tt && tt <= 0xff)
CWP--;
else
changedCWP = false;
if (changedCWP) {
CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP);
}
}
void
getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
{
//XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFF0000000ULL;
PC = RSTVAddr | ((TT << 5) & 0xFF);
NPC = PC + sizeof(MachInst);
}
void
getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
{
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst);
}
void
getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
{
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
PC = (TBA & ~mask(15)) |
(TL > 1 ? (1 << 14) : 0) |
((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst);
}
void
SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
{
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
2006-06-06 23:32:21 +02:00
FaultBase::invoke(tc);
if (!FullSystem)
return;
countStat()++;
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
// We can refer to this to see what the trap level -was-, but something
// in the middle could change it in the regfile out from under us.
MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
Addr PC, NPC;
PrivilegeLevel current;
if (hpstate.hpriv)
current = Hyperprivileged;
else if (pstate.priv)
current = Privileged;
else
current = User;
PrivilegeLevel level = getNextLevel(current);
if (hpstate.red || (tl == MaxTL - 1)) {
getREDVector(5, PC, NPC);
doREDFault(tc, tt);
// This changes the hpstate and pstate, so we need to make sure we
// save the old version on the trap stack in doREDFault.
enterREDState(tc);
} else if (tl == MaxTL) {
panic("Should go to error state here.. crap\n");
// Do error_state somehow?
// Probably inject a WDR fault using the interrupt mechanism.
// What should the PC and NPC be set to?
} else if (tl > MaxPTL && level == Privileged) {
// guest_watchdog fault
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, 2);
} else if (level == Hyperprivileged ||
(level == Privileged && trapType() >= 384)) {
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, trapType());
} else {
doNormalFault(tc, trapType(), false);
getPrivVector(tc, PC, NPC, trapType(), tl + 1);
}
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
PCState pc;
pc.pc(PC);
pc.npc(NPC);
pc.nnpc(NPC + sizeof(MachInst));
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
}
void
PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// For SPARC, when a system is first started, there is a power
// on reset Trap which sets the processor into the following state.
// Bits that aren't set aren't defined on startup.
tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
tc->setMiscRegNoEffect(MISCREG_TT, trapType());
tc->setMiscReg(MISCREG_GL, MaxGL);
PSTATE pstate = 0;
pstate.pef = 1;
pstate.priv = 1;
tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
// Turn on red and hpriv, set everything else to 0
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
hpstate.red = 1;
hpstate.hpriv = 1;
hpstate.ibe = 0;
hpstate.tlz = 0;
tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
// The tick register is unreadable by nonprivileged software
tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
// Enter RED state. We do this last so that the actual state preserved in
// the trap stack is the state from before this fault.
enterREDState(tc);
Addr PC, NPC;
getREDVector(trapType(), PC, NPC);
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
PCState pc;
pc.pc(PC);
pc.npc(NPC);
pc.nnpc(NPC + sizeof(MachInst));
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
// These registers are specified as "undefined" after a POR, and they
// should have reasonable values after the miscregfile is reset
/*
// Clear all the soft interrupt bits
softint = 0;
// disable timer compare interrupts, reset tick_cmpr
tc->setMiscRegNoEffect(MISCREG_
tick_cmprFields.int_dis = 1;
tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
stickFields.npt = 1; // The TICK register is unreadable by by !priv
stick_cmprFields.int_dis = 1; // disable timer compare interrupts
stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
tt[tl] = _trapType;
hintp = 0; // no interrupts pending
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
*/
}
void
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
return;
}
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
if (!success) {
panic("Tried to execute unmapped address %#x.\n", vaddr);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, entry.pte);
}
}
void
FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
return;
}
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
if (!success) {
if (p->fixupStackFault(vaddr))
success = p->pTable->lookup(vaddr, entry);
}
if (!success) {
panic("Tried to access unmapped address %#x.\n", vaddr);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, entry.pte);
}
}
void
SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
return;
}
doNormalFault(tc, trapType(), false);
Process *p = tc->getProcessPtr();
//XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
// Then adjust the PC and NPC
tc->pcState(lp->readSpillStart());
}
void
FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
return;
}
doNormalFault(tc, trapType(), false);
Process *p = tc->getProcessPtr();
//XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
// Then adjust the PC and NPC
tc->pcState(lp->readFillStart());
}
void
TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
return;
}
// In SE, this mechanism is how the process requests a service from
// the operating system. We'll get the process object from the thread
// context and let it service the request.
Process *p = tc->getProcessPtr();
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
lp->handleTrap(_n, tc);
// We need to explicitly advance the pc, since that's not done for us
// on a faulting instruction
PCState pc = tc->pcState();
pc.advance();
tc->pcState(pc);
}
Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. arch/sparc/faults.cc: Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally. arch/sparc/faults.hh: Fix to have normal m5 line length limit, change pointers to const pointers. arch/sparc/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/sparc/faults.hh: ur Using cleaned up fault class deiffinitions arch/sparc/faults.hh: Added typedef for Addr arch/sparc/faults.hh: Made Addr a global type arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed Fault to be a RefCountingPtr arch/sparc/faults.cc: arch/sparc/faults.hh: MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. arch/sparc/faults.cc: arch/sparc/faults.hh: Put the Alpha faults into the AlphaISA namespace arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context. arch/sparc/faults.cc: AlphaFault is now an abstract class. arch/sparc/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. arch/sparc/faults.cc: arch/sparc/faults.hh: moved ev5_trap fully into the fault class. arch/sparc/faults.cc: arch/sparc/faults.hh: Changed the name of the fault's invocation method from ev5_trap to invoke. arch/sparc/faults.cc: arch/sparc/faults.hh: Moved the fault invocation code into the fault class fully, and got rid of the need for isA. arch/sparc/faults.cc: arch/sparc/faults.hh: Got rid of the multiple inheritance in the Fault classes, and the base MachineCheck and Alignment faults. arch/sparc/faults.cc: bk cp ../alpha/faults.cc faults.cc arch/sparc/faults.hh: bk cp ../alpha/faults.hh faults.hh SConscript: Moved the alpha specific source files into the alpha specific SConscript arch/alpha/SConscript: Moved the alpha specific source files into the alpha specific SConscript, and moved the process files into the new os specific subfolders. arch/alpha/linux/process.cc: arch/alpha/process.hh: arch/sparc/process.hh: arch/alpha/tru64/process.cc: Changed the include paths to use the new os specific directories. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/linux_process.hh => arch/alpha/linux/process.hh rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc rename : arch/alpha/tru64_process.hh => arch/alpha/tru64/process.hh rename : arch/sparc/linux_process.cc => arch/sparc/linux/process.cc rename : arch/sparc/linux_process.hh => arch/sparc/linux/process.hh extra : convert_revision : dc7eed7994b9c5e7308c771f43758292e78ce3e3
2006-03-07 10:25:42 +01:00
} // namespace SparcISA