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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 2.548434 # Number of seconds simulated
sim_ticks 2548433543500 # Number of ticks simulated
final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 62524 # Simulator instruction rate (inst/s)
host_op_rate 80452 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2641694597 # Simulator tick rate (ticks/s)
host_mem_usage 403600 # Number of bytes of host memory used
host_seconds 964.70 # Real time elapsed on the host
sim_insts 60316814 # Number of instructions simulated
sim_ops 77611972 # Number of ops (including micro ops) simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory
system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory
system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293431 # Total number of read requests seen
system.physmem.writeReqs 813143 # Total number of write requests seen
system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978779584 # Total number of bytes read from memory
system.physmem.bytesWritten 52041152 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry
system.physmem.totGap 2548432371500 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::2 42 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 154573 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::2 754025 # Categorize write packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::6 59118 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation
system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests
system.physmem.totBusLat 76467100000 # Total cycles spent in databus access
system.physmem.totBankLat 15405417500 # Total cycles spent in bank access
system.physmem.avgQLat 20197.04 # Average queueing delay per request
system.physmem.avgBankLat 1007.32 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgMemAccLat 26204.36 # Average memory access latency
system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 3.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
system.physmem.avgWrQLen 1.10 # Average write queue length over time
system.physmem.readRowHits 15267875 # Number of row buffer hits during reads
system.physmem.writeRowHits 798648 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes
system.physmem.avgGap 158223.12 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55014580 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16346067 # Transaction distribution
system.membus.trans_dist::ReadResp 16346070 # Transaction distribution
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
system.membus.trans_dist::Writeback 59118 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution
system.membus.trans_dist::ReadExReq 131411 # Transaction distribution
system.membus.trans_dist::ReadExResp 131411 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 140201001 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.l2c.replacements 64346 # number of replacements
system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use
system.l2c.total_refs 1905385 # Total number of references to valid blocks.
system.l2c.sampled_refs 129735 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.686746 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_percent::cpu0.inst 0.070517 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.051196 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000240 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.054606 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.043756 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784669 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 33086 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6984 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 499528 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 184262 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 30366 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6676 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 472129 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 203355 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1436386 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits
system.l2c.Writeback_hits::total 608398 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 21 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57570 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 55424 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112994 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 33086 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6984 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 499528 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 241832 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 30366 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6676 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 472129 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 258779 # number of demand (read+write) hits
system.l2c.demand_hits::total 1549380 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 33086 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6984 # number of overall hits
system.l2c.overall_hits::cpu0.inst 499528 # number of overall hits
system.l2c.overall_hits::cpu0.data 241832 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 30366 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6676 # number of overall hits
system.l2c.overall_hits::cpu1.inst 472129 # number of overall hits
system.l2c.overall_hits::cpu1.data 258779 # number of overall hits
system.l2c.overall_hits::total 1549380 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 18 # number of ReadReq misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu0.inst 6786 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6144 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 22 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5600 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4553 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1547 # number of UpgradeReq misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_misses::cpu1.data 1367 # number of UpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_misses::total 2914 # number of UpgradeReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 70783 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 62396 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133179 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 18 # number of demand (read+write) misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu0.inst 6786 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 76927 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 22 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5600 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 66949 # number of demand (read+write) misses
system.l2c.demand_misses::total 156304 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 18 # number of overall misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu0.inst 6786 # number of overall misses
system.l2c.overall_misses::cpu0.data 76927 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 22 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5600 # number of overall misses
system.l2c.overall_misses::cpu1.data 66949 # number of overall misses
system.l2c.overall_misses::total 156304 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1745000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 504819500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 454994499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1910500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 410434000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 342510500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1716543999 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 228000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 251000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 479000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4858356000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4267377000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9125733000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 1745000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 130000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 504819500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5313350499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1910500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 410434000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4609887500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 10842276999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 1745000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 130000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 504819500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5313350499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1910500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 410434000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4609887500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 10842276999 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 33104 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 6986 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 506314 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 190406 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 30388 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6676 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 477729 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 207908 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1459511 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 608398 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 608398 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1568 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1382 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 128353 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 117820 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246173 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 33104 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6986 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 506314 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 318759 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 30388 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6676 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 477729 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 325728 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1705684 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 33104 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6986 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 506314 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 318759 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 30388 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6676 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 477729 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 325728 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1705684 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000286 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013403 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.032268 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011722 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.021899 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015844 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986607 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989146 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.987797 # miss rate for UpgradeReq accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.200000 # miss rate for SCUpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.551471 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.529588 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.540998 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000286 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013403 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.241333 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011722 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.205537 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091637 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000286 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013403 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.241333 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011722 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.205537 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091637 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96944.444444 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74391.320365 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74055.094238 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86840.909091 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73291.785714 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75227.432462 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74228.929686 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 147.382030 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 183.613753 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 164.378861 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68637.328172 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68391.836015 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 68522.312076 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96944.444444 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 74391.320365 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69070.033915 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86840.909091 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73291.785714 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 68856.704357 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69366.599697 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96944.444444 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 74391.320365 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69070.033915 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86840.909091 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73291.785714 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 68856.704357 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69366.599697 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.writebacks::writebacks 59118 # number of writebacks
system.l2c.writebacks::total 59118 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 41 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 41 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 41 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 18 # number of ReadReq MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 6782 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6103 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 22 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 5592 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4528 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1547 # number of UpgradeReq MSHR misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1367 # number of UpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_misses::total 2914 # number of UpgradeReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 70783 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 62396 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 18 # number of demand (read+write) MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 6782 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 76886 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 22 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 5592 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 66924 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156226 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 18 # number of overall MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 6782 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 76886 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 22 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 5592 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 66924 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156226 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1520750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 420212000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 376397249 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1636250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 340379000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 284301250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1424552249 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15478046 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13672367 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29150413 # number of UpgradeReq MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3973988207 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3487056311 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7461044518 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1520750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 420212000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4350385456 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1636250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 340379000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3771357561 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8885596767 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1520750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 420212000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4350385456 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1636250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 340379000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3771357561 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8885596767 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6781750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 82698758000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 84243559500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166949099250 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 13398896029 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 10148159249 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 23547055278 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6781750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96097654029 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94391718749 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190496154528 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032053 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021779 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986607 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989146 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.987797 # mshr miss rate for UpgradeReq accesses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551471 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.529588 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.540998 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091591 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091591 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61674.135507 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62787.378534 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61810.745390 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.201034 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.731529 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.throughput 58505331 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 148893553 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48461480 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 123500861 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu0.branchPred.lookups 7472736 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.read_hits 25723416 # DTB read hits
system.cpu0.dtb.read_misses 39440 # DTB read misses
system.cpu0.dtb.write_hits 6006462 # DTB write hits
system.cpu0.dtb.write_misses 9528 # DTB write misses
system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 25762856 # DTB read accesses
system.cpu0.dtb.write_accesses 6015990 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.hits 31729878 # DTB hits
system.cpu0.dtb.misses 48968 # DTB misses
system.cpu0.dtb.accesses 31778846 # DTB accesses
system.cpu0.itb.inst_hits 6261683 # ITB inst hits
system.cpu0.itb.inst_misses 7235 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses
system.cpu0.itb.hits 6261683 # DTB hits
system.cpu0.itb.misses 7235 # DTB misses
system.cpu0.itb.accesses 6268918 # DTB accesses
system.cpu0.numCycles 237920120 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued
system.cpu0.iq.rate 0.264111 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.exec_nop 123681 # number of nop insts executed
system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5821167 # Number of branches executed
system.cpu0.iew.exec_stores 6250185 # Number of stores executed
system.cpu0.iew.exec_rate 0.258616 # Inst execution rate
system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 23943541 # num instructions producing a value
system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 30629038 # Number of instructions committed
system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.refs 13932896 # Number of memory references committed
system.cpu0.commit.loads 7948043 # Number of loads committed
system.cpu0.commit.membars 201908 # Number of memory barriers committed
system.cpu0.commit.branches 4992421 # Number of branches committed
system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions.
system.cpu0.commit.function_calls 490811 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.rob.rob_reads 124149615 # The number of ROB reads
system.cpu0.rob.rob_writes 103265708 # The number of ROB writes
system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 30545540 # Number of Instructions Simulated
system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated
system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads
system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes
system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads
system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes
system.cpu0.icache.replacements 984632 # number of replacements
system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use
system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5203197 # number of overall hits
system.cpu0.icache.overall_hits::total 10914069 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 548607 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 517852 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1066459 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 548607 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 517852 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1066459 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 548607 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 517852 # number of overall misses
system.cpu0.icache.overall_misses::total 1066459 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7528963984 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41633 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39659 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 81292 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 41633 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39659 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 81292 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 41633 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39659 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 81292 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 506974 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 478193 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 985167 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 506974 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 478193 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 985167 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 506974 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 478193 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 985167 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6125840118 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721520916 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11847361034 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6125840118 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5721520916 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11847361034 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6125840118 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5721520916 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11847361034 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9172000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9172000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9172000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 9172000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.080993 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083585 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.082231 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.080993 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083585 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.082231 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.080993 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083585 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.082231 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12083.144536 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11964.878022 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12025.738818 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12083.144536 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11964.878022 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12025.738818 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12083.144536 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11964.878022 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12025.738818 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.replacements 643975 # number of replacements
system.cpu0.dcache.tagsinuse 511.992067 # Cycle average of tags in use
system.cpu0.dcache.total_refs 21534411 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 644487 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.413259 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 48810000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 193.724997 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 318.267071 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.378369 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.621615 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7114161 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6663960 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13778121 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3647393 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3614436 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 7261829 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114620 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129061 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243681 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116531 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131145 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247676 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10761554 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10278396 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21039950 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10761554 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10278396 # number of overall hits
system.cpu0.dcache.overall_hits::total 21039950 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 340518 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 408477 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 748995 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1561577 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1400471 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2962048 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6933 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6630 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13563 # number of LoadLockedReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1902095 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1808948 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3711043 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1902095 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1808948 # number of overall misses
system.cpu0.dcache.overall_misses::total 3711043 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5421439000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6015207500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11436646500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76471634301 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 66135076354 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 142606710655 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98609000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 88268000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 186877000 # number of LoadLockedReq miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 77000 # number of StoreCondReq miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 77000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 154000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 81893073301 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 72150283854 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 154043357155 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 81893073301 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 72150283854 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 154043357155 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7454679 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7072437 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14527116 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208970 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5014907 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10223877 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121553 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135691 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 257244 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116536 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131150 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247686 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12663649 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12087344 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24750993 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12663649 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12087344 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24750993 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045678 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057756 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051558 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.299786 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.279262 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289719 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057037 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048861 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052724 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000043 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000038 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150201 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149656 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149935 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150201 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149656 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149935 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15921.152479 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14725.939282 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15269.322893 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48970.773968 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47223.452934 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48144.631908 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14223.135728 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13313.423831 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13778.441348 # average LoadLockedReq miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15400 # average StoreCondReq miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15400 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43054.144667 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39885.217184 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41509.450889 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43054.144667 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 39885.217184 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41509.450889 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 37642 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 26512 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3481 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 294 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.813559 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 90.176871 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.writebacks::writebacks 608398 # number of writebacks
system.cpu0.dcache.writebacks::total 608398 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 156322 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 206439 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 362761 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1431703 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1281330 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2713033 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 676 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 699 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1375 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1588025 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1487769 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3075794 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1588025 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1487769 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3075794 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184196 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 202038 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386234 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 129874 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119141 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 249015 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6257 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5931 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 314070 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 321179 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 635249 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 314070 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 321179 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 635249 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2559621550 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2682909890 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5242531440 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5713299541 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5062841611 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10776141152 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 77981002 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68096502 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146077504 # number of LoadLockedReq MSHR miss cycles
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 67000 # number of StoreCondReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 67000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8272921091 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7745751501 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16018672592 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8272921091 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7745751501 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.lookups 7176614 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_hits 25652921 # DTB read hits
system.cpu1.dtb.read_misses 36442 # DTB read misses
system.cpu1.dtb.write_hits 5708219 # DTB write hits
system.cpu1.dtb.write_misses 9483 # DTB write misses
system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25689363 # DTB read accesses
system.cpu1.dtb.write_accesses 5717702 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.hits 31361140 # DTB hits
system.cpu1.dtb.misses 45925 # DTB misses
system.cpu1.dtb.accesses 31407065 # DTB accesses
system.cpu1.itb.inst_hits 5722854 # ITB inst hits
system.cpu1.itb.inst_misses 6790 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses
system.cpu1.itb.hits 5722854 # DTB hits
system.cpu1.itb.misses 6790 # DTB misses
system.cpu1.itb.accesses 5729644 # DTB accesses
system.cpu1.numCycles 238719781 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued
system.cpu1.iq.rate 0.256467 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.exec_nop 99212 # number of nop insts executed
system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5705434 # Number of branches executed
system.cpu1.iew.exec_stores 5976719 # Number of stores executed
system.cpu1.iew.exec_rate 0.252085 # Inst execution rate
system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 23216135 # num instructions producing a value
system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 29838157 # Number of instructions committed
system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.refs 13458430 # Number of memory references committed
system.cpu1.commit.loads 7709539 # Number of loads committed
system.cpu1.commit.membars 201879 # Number of memory barriers committed
system.cpu1.commit.branches 4970440 # Number of branches committed
system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions.
system.cpu1.commit.function_calls 500692 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.rob.rob_reads 120414089 # The number of ROB reads
system.cpu1.rob.rob_writes 97409741 # The number of ROB writes
system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 29771274 # Number of Instructions Simulated
system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated
system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads
system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes
system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads
system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink