2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-05-23 17:59:13 +02:00
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sim_seconds 0.566012 # Number of seconds simulated
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sim_ticks 566011920000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-05-23 17:59:13 +02:00
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host_inst_rate 52057 # Simulator instruction rate (inst/s)
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host_tick_rate 17100212 # Simulator tick rate (ticks/s)
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host_mem_usage 255500 # Number of bytes of host memory used
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host_seconds 33099.70 # Real time elapsed on the host
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sim_insts 1723073884 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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system.cpu.numCycles 1132023841 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 287218932 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 236434259 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 18348095 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 250920104 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 213740165 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 18278609 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 393 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 265451297 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2081730004 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 287218932 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 232018774 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 452716467 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 20281434 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 265451297 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 5801201 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1120688032 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.061143 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.942664 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::0 667971623 59.60% 59.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 32961041 2.94% 62.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 55903718 4.99% 67.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 56895013 5.08% 72.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 45557119 4.07% 76.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 54242890 4.84% 81.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 48750643 4.35% 85.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 18749981 1.67% 87.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 139656004 12.46% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::total 1120688032 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.253722 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.838945 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 546126816 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 71463989 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 435974123 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 6702645 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 60420459 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 43189829 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 635 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2259641783 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2302 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 60420459 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 563998095 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 40175582 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 14256 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 424146965 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 31932675 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2194117520 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 11722 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 3482918 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 25684334 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 2171048745 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 10125608138 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 10125607580 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 558 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1706320007 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 464728733 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 633 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 629 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 66642282 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 598549667 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 212535274 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 87730642 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 84698913 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2112468775 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 616 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1975042527 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 852567 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 380766314 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 858455180 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1120688032 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.762348 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.680120 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 337912961 30.15% 30.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 234234895 20.90% 51.05% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 220010483 19.63% 70.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 141420525 12.62% 83.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 101836492 9.09% 92.39% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 53894209 4.81% 97.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 20983167 1.87% 99.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 9353324 0.83% 99.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1041976 0.09% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 1120688032 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IntAlu 517494 2.12% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 1 0.00% 2.12% # attempts to use FU when none available
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2011-05-14 00:29:27 +02:00
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::MemRead 23433886 96.11% 98.24% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 430313 1.76% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1219473147 61.74% 61.74% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1083372 0.05% 61.80% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 566098039 28.66% 90.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 188387953 9.54% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 1975042527 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.744700 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 24381694 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5096007233 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2495143403 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1922135162 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 114 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1999424161 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 34829517 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 112622888 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 463072 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1914554 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 37688221 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 273360 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewSquashCycles 60420459 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 18632955 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1195402 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2112469674 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 6157143 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 598549667 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 212535274 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 546 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 334650 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 56652 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1914554 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 16889121 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 3256921 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 20146042 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1946822051 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 556717785 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 28220476 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 283 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 742905406 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 235411550 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 186187621 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.719771 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1926889510 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1922135210 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1211916900 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 1896005064 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_rate 1.697964 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.639195 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 1723073902 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 389560093 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 464 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 18347567 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1060267574 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.625131 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.338631 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::0 472290035 44.54% 44.54% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 255203775 24.07% 68.61% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 110318720 10.40% 79.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 55061761 5.19% 84.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 28404469 2.68% 86.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 27943387 2.64% 89.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 20897685 1.97% 91.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 17855453 1.68% 93.18% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 72292289 6.82% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::total 1060267574 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 1723073902 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 660773831 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 485926778 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 213462372 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.bw_lim_events 72292289 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.rob.rob_reads 3100608681 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4285815110 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 696063 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 11335809 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1723073884 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1723073884 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.656979 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.656979 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.522118 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.522118 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 9738255749 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1902471542 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 36 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 2800450937 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 140 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 9 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 573.017722 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 265450383 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 717 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 370223.686192 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::0 573.017722 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.279794 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 265450383 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 265450383 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 265450383 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 914 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 914 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 914 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 32210500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 32210500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 32210500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 265451297 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 265451297 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 265451297 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35241.247265 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35241.247265 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35241.247265 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 197 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 197 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 197 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 717 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 717 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 717 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 24697500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 24697500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 24697500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 9552367 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4082.984998 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 675087648 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 9556463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 70.641999 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 6495236000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4082.984998 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.996823 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 507131941 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 167955564 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 69 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 675087505 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 675087505 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 10254687 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 4630483 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 14885170 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 14885170 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 173914872000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 112892331168 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 286807203168 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 286807203168 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 517386628 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 69 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 689972675 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 689972675 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.026830 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.021574 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.021574 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 19267.983044 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 19267.983044 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 148361910 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 35813 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4142.683104 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 3126452 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 2590385 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 2738322 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 5328707 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 5328707 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 7664302 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1892161 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 9556463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 9556463 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 89320855000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 42428124877 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 131748979877 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 131748979877 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014813 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.013850 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.013850 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 2920822 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26404.864855 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7838163 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2948145 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.658676 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 129803245500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 15746.128543 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 10658.736312 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.480534 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.325279 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 5643332 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 3126452 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 980638 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 6623970 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 6623970 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2021685 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 911525 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2933210 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2933210 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 69338469500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31601923000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 100940392500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 100940392500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 7665017 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 3126452 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1892163 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 9557180 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 9557180 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.263755 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.481737 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.306912 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.306912 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34412.944351 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34412.944351 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 48964500 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 5689 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8606.872913 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 1216359 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2021675 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 911525 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2933200 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2933200 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 62968532000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28735558500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 91704090500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 91704090500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263753 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481737 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.306911 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.306911 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
