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gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
[root]
type=Root
children=system
dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
init_param=0
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
mem_mode=timing
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.bridge]
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
resp_size_a=16
resp_size_b=16
write_ack=false
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
[system.cpu0]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
checker=Null
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu0.tracer
trapLatency=13
wbDepth=1
wbWidth=8
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=1
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu0.dtb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
size=64
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList5]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList5.opList
[system.cpu0.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
[system.cpu0.fuPool.FUList6.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList6.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList
count=1
opList=system.cpu0.fuPool.FUList7.opList
[system.cpu0.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu0.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=1
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu0.interrupts]
type=AlphaInterrupts
[system.cpu0.itb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
size=48
[system.cpu0.tracer]
type=ExeTracer
[system.cpu1]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
checker=Null
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu1.tracer
trapLatency=13
wbDepth=1
wbWidth=8
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=1
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
[system.cpu1.dtb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
size=64
[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7
[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu1.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList4.opList
[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList5]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList5.opList
[system.cpu1.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
[system.cpu1.fuPool.FUList6.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList6.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList
count=1
opList=system.cpu1.fuPool.FUList7.opList
[system.cpu1.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu1.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=1000
max_miss_count=0
mshrs=4
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=1
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
[system.cpu1.interrupts]
type=AlphaInterrupts
[system.cpu1.itb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
size=48
[system.cpu1.tracer]
type=ExeTracer
[system.disk0]
type=IdeDisk
children=image
delay=1000000
driveID=master
image=system.disk0.image
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
image_file=
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
read_only=true
[system.disk2]
type=IdeDisk
children=image
delay=1000000
driveID=master
image=system.disk2.image
[system.disk2.image]
type=CowDiskImage
children=child
child=system.disk2.image.child
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
image_file=
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
read_only=false
table_size=65536
[system.disk2.image.child]
type=RawDiskImage
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
read_only=true
[system.intrctrl]
type=IntrControl
sys=system
[system.iobus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
addr_range=0:8589934591
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
assoc=8
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=50000
max_miss_count=0
mshrs=20
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=1
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
hash_delay=1
latency=10000
max_miss_count=0
mshrs=92
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
num_cpus=2
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
children=badaddr_responder
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
block_size=64
bus_id=1
clock=1000
header_cycles=1
responder_set=false
width=64
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
default=system.membus.badaddr_responder.pio
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
[system.membus.badaddr_responder]
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
type=IsaFake
pio_addr=0
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
pio_latency=1000
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
pio_size=8
platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default
[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.port[1]
[system.simple_disk]
type=SimpleDisk
children=disk
disk=system.simple_disk.disk
system=system
[system.simple_disk.disk]
type=RawDiskImage
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
read_only=true
[system.terminal]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
intrctrl=system.intrctrl
system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
pio_latency=1000
platform=system.tsunami
system=system
terminal=system.terminal
pio=system.iobus.port[25]
[system.tsunami.cchip]
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[1]
[system.tsunami.ethernet]
type=NSGigE
BAR0=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR0LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR0Size=256
BAR1=0
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR1LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR1Size=4096
BAR2=0
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR2LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR2Size=0
BAR3=0
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR3LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR3Size=0
BAR4=0
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR4LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR4Size=0
BAR5=0
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR5LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR5Size=0
BIST=0
CacheLineSize=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=34
ExpansionROM=0
HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
MaximumLatency=52
MinimumGrant=176
ProgIF=0
Revision=0
Status=656
SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clock=0
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_no_allocate=true
dma_read_delay=0
dma_read_factor=0
dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=1000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
rx_filter=true
rx_thread=false
system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.fake_OROM]
type=IsaFake
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
pio_addr=8804615848432
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
pio_addr=8804615848304
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
pio_addr=8804615848569
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
pio_addr=8804615848451
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
pio_addr=8804615848515
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
pio_addr=8804615848579
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
pio_addr=8804615848643
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
pio_addr=8804615848707
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
pio_addr=8804615848771
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
pio_addr=8804615848835
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
pio_addr=8804615848899
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
pio_addr=8804615850617
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
pio_addr=8804615848891
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
pio_addr=8804615848816
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
pio_addr=8804615848696
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
pio_addr=8804615848936
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
pio_addr=8804615848680
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
pio_addr=8804615848944
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.port[7]
[system.tsunami.fb]
type=BadDevice
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
platform=system.tsunami
system=system
pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
BAR0=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR0LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR0Size=8
BAR1=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR1LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR1Size=4
BAR2=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR2LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR2Size=8
BAR3=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR3LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR3Size=4
BAR4=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR4LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR4Size=16
BAR5=1
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
BAR5LegacyIO=false
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
BAR5Size=0
BIST=0
CacheLineSize=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
MaximumLatency=0
MinimumGrant=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
disks=system.disk0 system.disk2
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.io]
type=TsunamiIO
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
platform=system.tsunami
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]
[system.tsunami.pchip]
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[2]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
pio_latency=1
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
pio_addr=8804615848952
pio_latency=1000
platform=system.tsunami
system=system
terminal=system.terminal
pio=system.iobus.port[24]
Reference in a new issue Copy permalink