2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2011-03-18 01:20:22 +01:00
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sim_seconds 2.369902 # Number of seconds simulated
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sim_ticks 2369901960000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1407810 # Simulator instruction rate (inst/s)
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host_tick_rate 1780114775 # Simulator tick rate (ticks/s)
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host_mem_usage 224180 # Number of bytes of host memory used
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host_seconds 1331.32 # Real time elapsed on the host
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sim_insts 1874244950 # Number of instructions simulated
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system.physmem.bytes_read 94696320 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 4230336 # Number of bytes written to this memory
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system.physmem.num_reads 1479630 # Number of read requests responded to by this memory
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system.physmem.num_writes 66099 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s)
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2010-11-08 20:59:35 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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system.cpu.numCycles 4739803920 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 1874244950 # Number of instructions executed
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system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
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system.cpu.num_func_calls 80344203 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1653698876 # number of integer instructions
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system.cpu.num_fp_insts 52289415 # number of float instructions
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system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
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system.cpu.num_mem_refs 908382480 # number of memory refs
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system.cpu.num_load_insts 631387182 # Number of load instructions
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system.cpu.num_store_insts 276995298 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 4739803920 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 18364 # number of replacements
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system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use
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system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
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2011-03-18 01:20:22 +01:00
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system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 1390251708 # number of overall hits
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system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
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system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 19803 # number of overall misses
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2010-09-22 08:07:35 +02:00
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system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.writebacks 0 # number of writebacks
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
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2010-09-22 08:07:35 +02:00
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system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
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2010-09-22 08:07:35 +02:00
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system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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2010-07-27 07:03:44 +02:00
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2012-01-25 18:19:50 +01:00
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 1529557 # number of replacements
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system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
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system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 895737439 # number of overall hits
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system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
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system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 1533653 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks 107259 # number of writebacks
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles
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|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 1478755 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 73826 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1479630 # number of overall misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses)
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses)
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
