2006-04-23 00:26:48 +02:00
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/*
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2013-01-07 19:05:46 +01:00
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* Copyright (c) 2011-2012 ARM Limited
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2012-01-17 19:55:08 +01:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-05-19 21:53:17 +02:00
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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2006-04-23 00:26:48 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-07 22:02:55 +02:00
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*
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* Authors: Korey Sewell
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2006-04-23 00:26:48 +02:00
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*/
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#ifndef __CPU_O3_LSQ_HH__
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#define __CPU_O3_LSQ_HH__
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#include <map>
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#include <queue>
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#include "cpu/o3/lsq_unit.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/inst_seq.hh"
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2006-06-03 00:15:20 +02:00
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#include "mem/port.hh"
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2006-04-23 00:26:48 +02:00
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#include "sim/sim_object.hh"
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2012-01-31 18:05:52 +01:00
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struct DerivO3CPUParams;
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2008-08-11 21:22:16 +02:00
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2006-04-23 00:26:48 +02:00
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template <class Impl>
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class LSQ {
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public:
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2006-06-16 23:08:47 +02:00
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typedef typename Impl::O3CPU O3CPU;
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2006-04-23 00:26:48 +02:00
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUPol::IEW IEW;
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typedef typename Impl::CPUPol::LSQUnit LSQUnit;
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2006-05-31 17:45:02 +02:00
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/** SMT policy. */
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2006-04-23 00:26:48 +02:00
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enum LSQPolicy {
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Dynamic,
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Partitioned,
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Threshold
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};
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/** Constructs an LSQ with the given parameters. */
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2008-08-11 21:22:16 +02:00
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LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
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2013-09-11 22:34:50 +02:00
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~LSQ() {
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if (thread) delete [] thread;
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}
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2006-04-23 00:26:48 +02:00
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/** Returns the name of the LSQ. */
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std::string name() const;
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2006-06-14 04:35:05 +02:00
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/** Registers statistics of each LSQ unit. */
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void regStats();
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2006-04-23 00:26:48 +02:00
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/** Sets the pointer to the list of active threads. */
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2009-05-26 18:23:13 +02:00
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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2013-01-07 19:05:46 +01:00
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/** Has the LSQ drained? */
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bool isDrained() const;
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2006-05-31 17:45:02 +02:00
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/** Takes over execution from another CPU's thread. */
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2006-05-04 17:36:20 +02:00
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void takeOverFrom();
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2006-04-23 00:26:48 +02:00
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/** Number of entries needed for the given amount of threads.*/
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2009-05-26 18:23:13 +02:00
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int entryAmount(ThreadID num_threads);
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void removeEntries(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/** Reset the max entries for each thread. */
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void resetEntries();
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/** Resize the max entries for a thread. */
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2009-05-26 18:23:13 +02:00
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void resizeEntries(unsigned size, ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/** Ticks the LSQ. */
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void tick();
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/** Ticks a specific LSQ Unit. */
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2009-05-26 18:23:13 +02:00
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void tick(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ thread[tid].tick(); }
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2006-04-23 00:26:48 +02:00
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/** Inserts a load into the LSQ. */
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void insertLoad(DynInstPtr &load_inst);
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/** Inserts a store into the LSQ. */
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void insertStore(DynInstPtr &store_inst);
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/** Executes a load. */
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Fault executeLoad(DynInstPtr &inst);
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/** Executes a store. */
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Fault executeStore(DynInstPtr &inst);
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/**
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* Commits loads up until the given sequence number for a specific thread.
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*/
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2009-05-26 18:23:13 +02:00
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void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ thread[tid].commitLoads(youngest_inst); }
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2006-04-23 00:26:48 +02:00
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/**
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* Commits stores up until the given sequence number for a specific thread.
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*/
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2009-05-26 18:23:13 +02:00
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void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ thread[tid].commitStores(youngest_inst); }
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2006-04-23 00:26:48 +02:00
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/**
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* Attempts to write back stores until all cache ports are used or the
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* interface becomes blocked.
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*/
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void writebackStores();
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/** Same as above, but only for one thread. */
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2009-05-26 18:23:13 +02:00
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void writebackStores(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/**
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* Squash instructions from a thread until the specified sequence number.
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*/
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2009-05-26 18:23:13 +02:00
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void squash(const InstSeqNum &squashed_num, ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ thread[tid].squash(squashed_num); }
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2006-04-23 00:26:48 +02:00
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/** Returns whether or not there was a memory ordering violation. */
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bool violation();
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/**
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* Returns whether or not there was a memory ordering violation for a
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* specific thread.
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*/
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2009-05-26 18:23:13 +02:00
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bool violation(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].violation(); }
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2006-04-23 00:26:48 +02:00
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/** Returns if a load is blocked due to the memory system for a specific
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* thread.
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*/
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2009-05-26 18:23:13 +02:00
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bool loadBlocked(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].loadBlocked(); }
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2006-04-23 00:26:48 +02:00
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2009-05-26 18:23:13 +02:00
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bool isLoadBlockedHandled(ThreadID tid)
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2006-04-23 00:26:48 +02:00
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{ return thread[tid].isLoadBlockedHandled(); }
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2009-05-26 18:23:13 +02:00
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void setLoadBlockedHandled(ThreadID tid)
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2006-04-23 00:26:48 +02:00
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{ thread[tid].setLoadBlockedHandled(); }
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/** Gets the instruction that caused the memory ordering violation. */
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2009-05-26 18:23:13 +02:00
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DynInstPtr getMemDepViolator(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].getMemDepViolator(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the head index of the load queue for a specific thread. */
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2009-05-26 18:23:13 +02:00
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int getLoadHead(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].getLoadHead(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the sequence number of the head of the load queue. */
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2009-05-26 18:23:13 +02:00
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InstSeqNum getLoadHeadSeqNum(ThreadID tid)
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2006-04-23 00:26:48 +02:00
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{
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return thread[tid].getLoadHeadSeqNum();
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}
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/** Returns the head index of the store queue. */
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2009-05-26 18:23:13 +02:00
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int getStoreHead(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].getStoreHead(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the sequence number of the head of the store queue. */
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2009-05-26 18:23:13 +02:00
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InstSeqNum getStoreHeadSeqNum(ThreadID tid)
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2006-04-23 00:26:48 +02:00
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{
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return thread[tid].getStoreHeadSeqNum();
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}
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/** Returns the number of instructions in all of the queues. */
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int getCount();
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/** Returns the number of instructions in the queues of one thread. */
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2009-05-26 18:23:13 +02:00
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int getCount(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].getCount(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the total number of loads in the load queue. */
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int numLoads();
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/** Returns the total number of loads for a single thread. */
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2009-05-26 18:23:13 +02:00
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int numLoads(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].numLoads(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the total number of stores in the store queue. */
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int numStores();
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/** Returns the total number of stores for a single thread. */
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2009-05-26 18:23:13 +02:00
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int numStores(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].numStores(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the number of free entries. */
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unsigned numFreeEntries();
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/** Returns the number of free entries for a specific thread. */
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2009-05-26 18:23:13 +02:00
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unsigned numFreeEntries(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/** Returns if the LSQ is full (either LQ or SQ is full). */
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bool isFull();
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/**
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* Returns if the LSQ is full for a specific thread (either LQ or SQ is
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* full).
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*/
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2009-05-26 18:23:13 +02:00
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bool isFull(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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2013-01-07 19:05:46 +01:00
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/** Returns if the LSQ is empty (both LQ and SQ are empty). */
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bool isEmpty() const;
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/** Returns if all of the LQs are empty. */
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bool lqEmpty() const;
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/** Returns if all of the SQs are empty. */
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bool sqEmpty() const;
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2006-04-23 00:26:48 +02:00
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/** Returns if any of the LQs are full. */
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bool lqFull();
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/** Returns if the LQ of a given thread is full. */
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2009-05-26 18:23:13 +02:00
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bool lqFull(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/** Returns if any of the SQs are full. */
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bool sqFull();
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/** Returns if the SQ of a given thread is full. */
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2009-05-26 18:23:13 +02:00
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bool sqFull(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/**
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* Returns if the LSQ is stalled due to a memory operation that must be
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* replayed.
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*/
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bool isStalled();
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/**
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* Returns if the LSQ of a specific thread is stalled due to a memory
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* operation that must be replayed.
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*/
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2009-05-26 18:23:13 +02:00
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bool isStalled(ThreadID tid);
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2006-04-23 00:26:48 +02:00
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/** Returns whether or not there are any stores to write back to memory. */
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bool hasStoresToWB();
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2006-05-19 21:53:17 +02:00
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2006-04-23 00:26:48 +02:00
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/** Returns whether or not a specific thread has any stores to write back
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* to memory.
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*/
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2009-05-26 18:23:13 +02:00
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bool hasStoresToWB(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].hasStoresToWB(); }
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2006-04-23 00:26:48 +02:00
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/** Returns the number of stores a specific thread has to write back. */
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2009-05-26 18:23:13 +02:00
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int numStoresToWB(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].numStoresToWB(); }
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2006-04-23 00:26:48 +02:00
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/** Returns if the LSQ will write back to memory this cycle. */
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bool willWB();
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/** Returns if the LSQ of a specific thread will write back to memory this
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* cycle.
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*/
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2009-05-26 18:23:13 +02:00
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bool willWB(ThreadID tid)
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2006-05-19 21:53:17 +02:00
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{ return thread[tid].willWB(); }
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2006-04-23 00:26:48 +02:00
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2006-07-13 19:12:51 +02:00
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/** Returns if the cache is currently blocked. */
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2013-01-07 19:05:46 +01:00
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bool cacheBlocked() const
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2009-05-26 18:23:13 +02:00
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{ return retryTid != InvalidThreadID; }
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2006-07-13 19:12:51 +02:00
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/** Sets the retry thread id, indicating that one of the LSQUnits
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* tried to access the cache but the cache was blocked. */
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2009-05-26 18:23:13 +02:00
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void setRetryTid(ThreadID tid)
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2006-07-13 19:12:51 +02:00
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{ retryTid = tid; }
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2006-04-23 00:26:48 +02:00
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/** Debugging function to print out all instructions. */
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2013-01-07 19:05:46 +01:00
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void dumpInsts() const;
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2006-04-23 00:26:48 +02:00
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/** Debugging function to print out instructions from a specific thread. */
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2013-01-07 19:05:46 +01:00
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void dumpInsts(ThreadID tid) const
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2006-05-19 21:53:17 +02:00
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{ thread[tid].dumpInsts(); }
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2006-04-23 00:26:48 +02:00
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2010-02-12 20:53:20 +01:00
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/** Executes a read operation, using the load specified at the load
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* index.
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*/
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Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
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2010-08-13 15:16:02 +02:00
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uint8_t *data, int load_idx);
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2006-04-23 00:26:48 +02:00
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/** Executes a store operation, using the store specified at the store
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2010-02-12 20:53:20 +01:00
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* index.
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2006-04-23 00:26:48 +02:00
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*/
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2010-02-12 20:53:20 +01:00
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Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
|
2010-08-13 15:16:02 +02:00
|
|
|
uint8_t *data, int store_idx);
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2012-01-17 19:55:08 +01:00
|
|
|
/**
|
|
|
|
* Retry the previous send that failed.
|
|
|
|
*/
|
|
|
|
void recvRetry();
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Handles writing back and completing the load or store that has
|
|
|
|
* returned from memory.
|
|
|
|
*
|
|
|
|
* @param pkt Response packet from the memory sub-system
|
|
|
|
*/
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
bool recvTimingResp(PacketPtr pkt);
|
2012-01-17 19:55:08 +01:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
void recvTimingSnoopReq(PacketPtr pkt);
|
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
|
|
|
|
2007-04-04 21:38:59 +02:00
|
|
|
/** The CPU pointer. */
|
|
|
|
O3CPU *cpu;
|
|
|
|
|
|
|
|
/** The IEW stage pointer. */
|
|
|
|
IEW *iewStage;
|
|
|
|
|
2006-07-13 19:12:51 +02:00
|
|
|
protected:
|
2006-04-23 00:26:48 +02:00
|
|
|
/** The LSQ policy for SMT mode. */
|
|
|
|
LSQPolicy lsqPolicy;
|
|
|
|
|
|
|
|
/** The LSQ units for individual threads. */
|
2013-09-11 22:34:50 +02:00
|
|
|
LSQUnit *thread;
|
2006-04-23 00:26:48 +02:00
|
|
|
|
|
|
|
/** List of Active Threads in System. */
|
2009-05-26 18:23:13 +02:00
|
|
|
std::list<ThreadID> *activeThreads;
|
2006-04-23 00:26:48 +02:00
|
|
|
|
|
|
|
/** Total Size of LQ Entries. */
|
|
|
|
unsigned LQEntries;
|
|
|
|
/** Total Size of SQ Entries. */
|
|
|
|
unsigned SQEntries;
|
|
|
|
|
|
|
|
/** Max LQ Size - Used to Enforce Sharing Policies. */
|
|
|
|
unsigned maxLQEntries;
|
|
|
|
|
|
|
|
/** Max SQ Size - Used to Enforce Sharing Policies. */
|
|
|
|
unsigned maxSQEntries;
|
|
|
|
|
|
|
|
/** Number of Threads. */
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID numThreads;
|
2006-07-13 19:12:51 +02:00
|
|
|
|
|
|
|
/** The thread id of the LSQ Unit that is currently waiting for a
|
|
|
|
* retry. */
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID retryTid;
|
2006-04-23 00:26:48 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
2010-02-12 20:53:20 +01:00
|
|
|
LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
|
2010-08-13 15:16:02 +02:00
|
|
|
uint8_t *data, int load_idx)
|
2006-04-23 00:26:48 +02:00
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID tid = req->threadId();
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2010-02-12 20:53:20 +01:00
|
|
|
return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
2010-02-12 20:53:20 +01:00
|
|
|
LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
|
2010-08-13 15:16:02 +02:00
|
|
|
uint8_t *data, int store_idx)
|
2006-04-23 00:26:48 +02:00
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID tid = req->threadId();
|
2006-04-23 00:26:48 +02:00
|
|
|
|
2010-02-12 20:53:20 +01:00
|
|
|
return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
|
2006-04-23 00:26:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif // __CPU_O3_LSQ_HH__
|