2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.708531 # Number of seconds simulated
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sim_ticks 708531477500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 73177 # Simulator instruction rate (inst/s)
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host_tick_rate 27500789 # Simulator tick rate (ticks/s)
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host_mem_usage 269872 # Number of bytes of host memory used
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host_seconds 25764.04 # Real time elapsed on the host
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2011-08-19 22:08:08 +02:00
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sim_insts 1885333781 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 1417062956 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 503197532 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 388248962 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 32912455 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 402367124 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 282669140 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.usedRAS 59794264 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2845178 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 410598466 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2543215501 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 503197532 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 342463404 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 683221197 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 205184289 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 105176674 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2131 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 34940 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 384286264 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 12168665 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1365728364 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.589436 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.160278 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 682546834 49.98% 49.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 48268776 3.53% 53.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 108820649 7.97% 61.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 62416445 4.57% 66.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 89329433 6.54% 72.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 54222188 3.97% 76.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 35559819 2.60% 79.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 34994936 2.56% 81.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 249569284 18.27% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 1365728364 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.355099 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.794709 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 455451885 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 84966420 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 647527818 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 11100617 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 166681624 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 68771353 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 13534 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3425616416 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 23343 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 166681624 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 496974681 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 29107016 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 3577336 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 615567899 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 53819808 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3299332882 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4545741 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 42264080 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3261811960 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 15630618087 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 14995522132 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 635095955 # Number of floating rename lookups
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 1268658364 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 292165 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 287873 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 155635348 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1045682058 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 527865899 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 35886161 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 45188431 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3078949788 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 286075 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2620068122 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 18730048 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1193263945 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 2902703474 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 76157 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1365728364 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.918440 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.900398 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 480776818 35.20% 35.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 182697295 13.38% 48.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 216773103 15.87% 64.45% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 179469890 13.14% 77.59% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 151098316 11.06% 88.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 89760948 6.57% 95.23% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 48715298 3.57% 98.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 11568409 0.85% 99.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 4868287 0.36% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 1365728364 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 2047633 2.26% 2.26% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23928 0.03% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 55695213 61.39% 63.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 32952568 36.32% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1201100528 45.84% 45.84% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 11234357 0.43% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 6823 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876481 0.26% 46.59% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5505298 0.21% 46.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 24361440 0.93% 47.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 896104682 34.20% 81.93% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 473503224 18.07% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2620068122 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.848943 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 90719342 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.034625 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 6586805397 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 4173231874 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2409969161 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 128508601 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 99321062 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57077308 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2645158963 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 65628501 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 72009285 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 414293189 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 264533 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1389891 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 250868916 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 87 # Number of loads that were rescheduled
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 166681624 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16374995 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1474320 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3079304358 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 12740517 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1045682058 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 527865899 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 274568 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1470984 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 216 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1389891 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 34543873 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 8891706 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 43435579 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2534937994 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 842579419 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 85130128 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 68495 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1294824342 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 344662618 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 452244923 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.788868 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2496106713 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 2467046469 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1448587293 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2708320532 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.740958 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.534866 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 1193920948 # The number of squashed insts skipped by commit
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 38436982 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1199046742 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.572370 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.256600 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 532251438 44.39% 44.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 299124354 24.95% 69.34% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 106727923 8.90% 78.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 77554525 6.47% 84.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 53347084 4.45% 89.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 23351353 1.95% 91.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 17117984 1.43% 92.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 9328631 0.78% 93.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 80243450 6.69% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1199046742 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.count 1885344797 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 908385851 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 631388868 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 291350231 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 80243450 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 4198050692 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 6325233568 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1340861 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 51334592 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.committedInsts 1885333781 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.cpi 0.751624 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.751624 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.330452 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.330452 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12569578143 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2360113760 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 68800138 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 50190994 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 3981621400 # number of misc regfile reads
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.replacements 27318 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1634.845440 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 384252011 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 28994 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 13252.811306 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1634.845440 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.798264 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 384252124 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 384252124 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 384252124 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 34140 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 34140 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 34140 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 301222000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 301222000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 301222000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 384286264 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 384286264 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 384286264 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 8823.140012 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 8823.140012 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 8823.140012 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 774 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 774 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 774 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 33366 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 33366 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 33366 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 180870500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 180870500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 180870500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5420.802613 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 1531930 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.787279 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1029517706 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1536026 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 670.247578 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 306646000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4094.787279 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999704 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 753359421 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 276118539 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 14346 # number of LoadLockedReq hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_hits 1029477960 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 1029477960 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1938279 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 817139 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_misses 2755418 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2755418 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 69353392500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 28486542000 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 97839934500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 97839934500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 755297700 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 14349 # number of LoadLockedReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 1032233378 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 1032233378 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000209 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35780.913119 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 34861.317352 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 35508.200389 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 35508.200389 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 106827 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 474953 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 740066 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 1215019 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1215019 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1463326 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 77073 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1540399 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1540399 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 50026128000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2483951500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 52510079500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 52510079500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34186.591368 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32228.556044 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 1480043 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31970.970884 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 85321 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1512763 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.056401 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 29004.040754 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 2966.930131 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.885133 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.090544 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 76995 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 106827 # number of Writeback hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 83615 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 83615 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1415326 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 4368 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 1481407 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1481407 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 48560731500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2252343000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 50813074500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 50813074500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1492321 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 106827 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 4372 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 72701 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1565022 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1565022 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.948406 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.999085 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908942 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.946573 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.946573 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34310.633381 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.578018 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34300.549748 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34300.549748 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 66098 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 25 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 25 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1415301 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 4368 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1481382 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1481382 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43971676000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 135408000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048571000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 46020247000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 46020247000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948389 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999085 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908942 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.946557 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.946557 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.780422 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.907977 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
