2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.721574 # Number of seconds simulated
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sim_ticks 721574387500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 93472 # Simulator instruction rate (inst/s)
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host_tick_rate 35774469 # Simulator tick rate (ticks/s)
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host_mem_usage 269932 # Number of bytes of host memory used
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host_seconds 20170.09 # Real time elapsed on the host
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sim_insts 1885333781 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 1443148776 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 514101790 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 393960342 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 32849417 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 411992130 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 292369997 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 61143344 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2847666 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 422838137 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2603354590 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 514101790 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 353513341 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 695385496 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 212683081 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 100667444 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 34744 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 396353337 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 13400662 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1391803250 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.587957 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.156576 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 696457133 50.04% 50.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 48140413 3.46% 53.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 109472309 7.87% 61.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 63203054 4.54% 65.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 93420590 6.71% 72.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 55467471 3.99% 76.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 38010894 2.73% 79.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 34903580 2.51% 81.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 252727806 18.16% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 1391803250 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.356236 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.803941 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 467512838 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 82010941 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 659587023 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9830183 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 172862265 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 71310699 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 13247 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3482203473 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 23181 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 172862265 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 507308890 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 29017787 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 3569068 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 628144166 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 50901074 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3355358425 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4098898 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 41311851 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3338398637 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 15926092867 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 15179476932 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 746615935 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 1345245041 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 293826 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 289544 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 148458476 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1060445315 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 528215229 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 34855006 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 42545066 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3129553839 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 287167 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2641710303 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 18698476 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1243985610 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 3101856113 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 77249 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1391803250 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.898049 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.895078 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 496637821 35.68% 35.68% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 187318392 13.46% 49.14% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 216683253 15.57% 64.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 183278078 13.17% 77.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 154759947 11.12% 89.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 88115850 6.33% 95.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 48435610 3.48% 98.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 11635919 0.84% 99.65% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 4938380 0.35% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 1391803250 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 2241949 2.46% 2.46% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23931 0.03% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 55591183 61.06% 63.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 33183599 36.45% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1209438891 45.78% 45.78% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 11231174 0.43% 46.21% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 6786 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876480 0.26% 46.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5505922 0.21% 46.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 24487735 0.93% 47.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 908321415 34.38% 82.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 474466611 17.96% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2641710303 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.830518 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 91040662 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.034463 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 6653435449 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 4251253883 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2425638071 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 131527545 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 124012557 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57076576 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2665613044 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 67137921 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 72083065 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 429056446 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 91786 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 2776714 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 251218246 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 172862265 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16375195 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1473977 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3129909418 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 11871497 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1060445315 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 528215229 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 275665 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1470985 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 210 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 2776714 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 34610253 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 8646611 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 43256864 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2550234981 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 850160020 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 91475322 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 68412 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1303401841 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 346693404 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 453241821 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.767132 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2511392174 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 2482714647 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1457352486 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2693773506 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.720346 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.541008 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 1244525975 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 38374226 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1218940987 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.546707 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.221520 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 542456201 44.50% 44.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 304987693 25.02% 69.52% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 110181944 9.04% 78.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 79585029 6.53% 85.09% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 53872031 4.42% 89.51% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 24566271 2.02% 91.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 17102531 1.40% 92.93% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 9210832 0.76% 93.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 76978455 6.32% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1218940987 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 1885344797 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 908385851 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 631388868 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 291350231 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 76978455 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 4271814959 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 6432618886 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1340911 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 51345526 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1885333781 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.765461 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.765461 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.306403 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.306403 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12650608214 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2377451435 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 68801235 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 50191358 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 4051722338 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 27265 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1631.022811 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 396319184 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 28937 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 13695.931990 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1631.022811 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.796398 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 396319190 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 396319190 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 396319190 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 34147 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 34147 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 34147 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 302756000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 302756000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 302756000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 396353337 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 396353337 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 396353337 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000086 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000086 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000086 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 8866.254722 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 8866.254722 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 8866.254722 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 858 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 858 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 858 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 33289 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 33289 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 33289 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 180196000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 180196000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 180196000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5413.079396 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 1531918 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.807844 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1037036260 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1536014 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 675.147661 # Average number of references to valid blocks.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 306953000 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 4094.807844 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999709 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 760874912 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 276118613 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 15353 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 1036993525 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 1036993525 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1940591 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 817065 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_misses 2757656 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2757656 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 69372468500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 28482649500 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 97855118000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 97855118000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 762815503 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 15356 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 1039751181 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 1039751181 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.002544 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.002950 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000195 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.002652 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.002652 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35748.114105 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 34859.710672 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 35484.889341 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 35484.889341 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 106488 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 477280 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 740009 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 1217289 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1217289 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1463311 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 77056 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1540367 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1540367 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 50023449500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2483285500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 52506735000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 52506735000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.001481 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.001481 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.111367 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32227.023204 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 1480007 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31971.458810 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 84947 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.056155 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 29004.872731 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 2966.586079 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.885158 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.090533 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 76859 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 106488 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 6622 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 83481 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 83481 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1415390 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 4348 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 1481472 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1481472 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 48557740000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2252374000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 50810114000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 50810114000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1492249 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 106488 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 4352 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 72704 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1564953 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1564953 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.948495 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.999081 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908918 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.946656 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.946656 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34306.968397 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.531340 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34297.046451 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34297.046451 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1415364 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 4348 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1481446 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1481446 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43973597000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134788000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048603500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 46022200500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 46022200500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948477 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999081 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908918 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.946639 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.946639 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.754751 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.930662 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
