2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:06 +02:00
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sim_seconds 0.774805 # Number of seconds simulated
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sim_ticks 774804895000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:06 +02:00
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host_inst_rate 78044 # Simulator instruction rate (inst/s)
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host_tick_rate 32073308 # Simulator tick rate (ticks/s)
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2011-07-10 19:56:09 +02:00
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host_mem_usage 264164 # Number of bytes of host memory used
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2011-08-19 22:08:06 +02:00
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host_seconds 24157.31 # Real time elapsed on the host
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sim_insts 1885341976 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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2011-08-19 22:08:06 +02:00
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system.cpu.numCycles 1549609791 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.lookups 528720404 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 405201149 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 32899214 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 420084737 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 301658852 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.usedRAS 69231604 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2844202 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 441882986 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2652302812 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 528720404 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 370890456 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 718660047 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 237987325 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 141427708 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 5060 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 410572411 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 11240316 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1497398135 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.463229 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.115993 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::0 778775531 52.01% 52.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 50816086 3.39% 55.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 117376582 7.84% 63.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 64268768 4.29% 67.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 98483271 6.58% 74.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 55328075 3.69% 77.80% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 42969714 2.87% 80.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 33373173 2.23% 82.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 256006935 17.10% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::total 1497398135 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.341196 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.711594 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 490492895 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 110799689 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 685856855 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 14839948 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 195408748 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 70149015 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 13528 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3592611687 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 23480 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 195408748 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 532538328 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 41527455 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 3530778 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 657203589 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 67189237 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3464582939 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 83 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4053070 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 53839616 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3447136427 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 16419760198 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 15673686759 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 746073439 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993166703 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 1453969719 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 280977 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 281142 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 192553677 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1121958053 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 549497958 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 186141114 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 133678303 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3274000051 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 286918 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2696986204 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 15942313 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1388610041 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 3416788899 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 75361 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1497398135 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.801115 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.821957 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::0 520879280 34.79% 34.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 250662816 16.74% 51.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 249981874 16.69% 68.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 183430350 12.25% 80.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 145558199 9.72% 90.19% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 90126006 6.02% 96.21% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 37572713 2.51% 98.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 15725690 1.05% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 3461207 0.23% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::total 1497398135 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.fu_full::IntAlu 466158 0.65% 0.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23952 0.03% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 43631235 60.82% 61.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 27621714 38.50% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1249934524 46.35% 46.35% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 15347152 0.57% 46.91% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 8678 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.97% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.97% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.25% 47.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5502225 0.20% 47.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 24546538 0.91% 48.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 926115609 34.34% 82.67% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 467279715 17.33% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2696986204 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.740429 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 71743059 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.026601 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 6850131362 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 4543112182 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2499696981 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 128924553 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 123913779 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57056788 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2702891798 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 65837465 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 68903819 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 490567545 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 34373 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 5468301 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 272499336 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 85 # Number of loads that were rescheduled
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 195408748 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16548936 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1477418 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3274352719 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 7542599 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1121958053 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 549497958 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 274197 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1475285 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 5468301 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 35960500 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 8891555 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 44852055 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2594017984 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 869263464 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 102968220 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.exec_nop 65750 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1311874105 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 351627111 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 442610641 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.673981 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 2572992074 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 2556753769 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1518871802 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2751373427 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.wb_rate 1.649934 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.552041 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1885352992 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 1388961384 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 211557 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 38421689 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1301989389 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.448056 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.137383 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 590521474 45.36% 45.36% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 345830520 26.56% 71.92% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 113709906 8.73% 80.65% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 73638275 5.66% 86.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 53779351 4.13% 90.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 24377206 1.87% 92.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 19730682 1.52% 93.82% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 7415491 0.57% 94.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 72986484 5.61% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1301989389 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 1885352992 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.refs 908389129 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 631390507 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.branches 291351870 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.int_insts 1653712175 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.bw_lim_events 72986484 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.rob.rob_reads 4503298936 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 6744049642 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1345030 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 52211656 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1885341976 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1885341976 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.821925 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.821925 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.216656 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.216656 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12929172445 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2454347411 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 68793732 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 50170083 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 4128169598 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 13779552 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 25756 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1635.277334 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 410544180 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 27432 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 14965.885827 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1635.277334 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.798475 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 410544181 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 410544181 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 410544181 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 28230 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 28230 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 28230 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 268370000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 268370000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 268370000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 410572411 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 410572411 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 410572411 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000069 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000069 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000069 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 9506.553312 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 9506.553312 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 9506.553312 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 792 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 792 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 792 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 27438 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 27438 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 27438 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 164813000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 164813000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 164813000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6006.742474 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 6006.742474 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 6006.742474 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.replacements 1531422 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.889747 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1060675603 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1535518 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 690.760775 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 306953000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4094.889747 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999729 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 784517362 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 276127149 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 17768 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 13310 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 1060644511 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 1060644511 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1932656 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 808529 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_misses 2741185 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2741185 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 69641234000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 28315172500 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 97956406500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 97956406500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 786450018 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 17771 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 13310 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 1063385696 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 1063385696 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.002457 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.002920 # miss rate for WriteReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000169 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.002578 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.002578 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 36033.952240 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35020.602229 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 35735.058560 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 35735.058560 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.writebacks 106530 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 469858 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 735802 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 1205660 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1205660 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1462798 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 72727 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1535525 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1535525 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 50071553500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2361380000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 52432933500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 52432933500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001860 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.001444 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.001444 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34229.984933 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.096759 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34146.584067 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34146.584067 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.replacements 1479883 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31974.412351 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 83096 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1512603 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.054936 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 29007.598549 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 2966.813802 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.885242 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.090540 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 75017 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 106530 # number of Writeback hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 6638 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 81655 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 81655 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1415213 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 66083 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 1481296 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1481296 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 48605841000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2279788500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 50885629500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 50885629500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1490230 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 106530 # number of Writeback accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 72721 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1562951 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1562951 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.949661 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908720 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.947756 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.947756 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34345.247676 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.865064 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34352.100796 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34352.100796 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 24 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 24 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 24 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1415189 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66083 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1481272 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1481272 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 44022928500 # number of ReadReq MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048636000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 46071564500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 46071564500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949645 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908720 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.947741 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.947741 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.455259 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.953347 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.703960 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.703960 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
