2009-10-27 17:24:39 +01:00
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Timothy M. Jones
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* Gabe Black
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* Stephen Hines
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*/
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#ifndef __ARCH_POWER_ISA_TRAITS_HH__
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#define __ARCH_POWER_ISA_TRAITS_HH__
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#include "arch/power/types.hh"
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#include "base/types.hh"
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2011-09-09 11:40:11 +02:00
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#include "cpu/static_inst_fwd.hh"
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2009-10-27 17:24:39 +01:00
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2011-01-03 23:35:43 +01:00
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namespace BigEndianGuest {}
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2009-10-27 17:24:39 +01:00
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namespace PowerISA
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{
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using namespace BigEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// POWER DOES NOT have a delay slot
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#define ISA_HAS_DELAY_SLOT 0
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const Addr PageShift = 12;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr Page_Mask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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const int MachineBytes = 4;
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2012-06-05 19:52:30 +02:00
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// This is ori 0, 0, 0
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const ExtMachInst NoopMachInst = 0x60000000;
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2009-10-27 17:24:39 +01:00
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2010-02-12 20:53:20 +01:00
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// Memory accesses can be unaligned
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const bool HasUnalignedMemAcc = true;
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2012-11-02 17:32:00 +01:00
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const bool CurThreadInfoImplemented = false;
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const int CurThreadInfoReg = -1;
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2011-01-03 23:35:43 +01:00
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} // namespace PowerISA
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2009-10-27 17:24:39 +01:00
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#endif // __ARCH_POWER_ISA_TRAITS_HH__
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