2009-05-11 19:38:43 +02:00
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*/
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2009-08-04 19:52:52 +02:00
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machine(Directory, "Directory protocol")
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2010-01-30 05:29:26 +01:00
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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int directory_latency = 6
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2009-08-04 19:52:52 +02:00
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{
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2009-05-11 19:38:43 +02:00
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// ** IN QUEUES **
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MessageBuffer foo1, network="From", virtual_network="0", ordered="false"; // a mod-L2 bank -> this Dir
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MessageBuffer requestToDir, network="From", virtual_network="1", ordered="false"; // a mod-L2 bank -> this Dir
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MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false"; // a mod-L2 bank -> this Dir
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2009-08-04 19:52:52 +02:00
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2009-05-11 19:38:43 +02:00
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MessageBuffer goo1, network="To", virtual_network="0", ordered="false";
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MessageBuffer forwardFromDir, network="To", virtual_network="1", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="2", ordered="false"; // Dir -> mod-L2 bank
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// STATES
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2011-02-24 01:41:59 +01:00
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state_declaration(State, desc="Directory states", default="Directory_State_I") {
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2009-05-11 19:38:43 +02:00
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// Base states
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2011-02-24 01:41:59 +01:00
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I, AccessPermission:Invalid, desc="Invalid";
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S, AccessPermission:Read_Only, desc="Shared";
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O, AccessPermission:Read_Only, desc="Owner";
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M, AccessPermission:Read_Write, desc="Modified";
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2009-05-11 19:38:43 +02:00
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2011-02-24 01:41:59 +01:00
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IS, AccessPermission:Busy, desc="Blocked, was in idle";
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SS, AccessPermission:Read_Only, desc="Blocked, was in shared";
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OO, AccessPermission:Read_Only, desc="Blocked, was in owned";
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MO, AccessPermission:Read_Only, desc="Blocked, going to owner or maybe modified";
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MM, AccessPermission:Read_Only, desc="Blocked, going to modified";
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MM_DMA, AccessPermission:Busy, desc="Blocked, going to I";
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2009-05-11 19:38:43 +02:00
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2011-02-24 01:41:59 +01:00
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MI, AccessPermission:Busy, desc="Blocked on a writeback";
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MIS, AccessPermission:Busy, desc="Blocked on a writeback, but don't remove from sharers when received";
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OS, AccessPermission:Busy, desc="Blocked on a writeback";
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OSS, AccessPermission:Busy, desc="Blocked on a writeback, but don't remove from sharers when received";
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2009-08-04 19:52:52 +02:00
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2011-02-24 01:41:59 +01:00
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XI_M, AccessPermission:Busy, desc="In a stable state, going to I, waiting for the memory controller";
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XI_U, AccessPermission:Busy, desc="In a stable state, going to I, waiting for an unblock";
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OI_D, AccessPermission:Busy, desc="In O, going to I, waiting for data";
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2009-05-11 19:38:43 +02:00
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}
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// Events
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enumeration(Event, desc="Directory events") {
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GETX, desc="A GETX arrives";
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GETS, desc="A GETS arrives";
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PUTX, desc="A PUTX arrives";
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PUTO, desc="A PUTO arrives";
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PUTO_SHARERS, desc="A PUTO arrives, but don't remove from sharers list";
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Unblock, desc="An unblock message arrives";
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Last_Unblock, desc="An unblock message arrives, we're not waiting for any additional unblocks";
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Exclusive_Unblock, desc="The processor become the exclusive owner (E or M) of the line";
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Clean_Writeback, desc="The final message as part of a PutX/PutS, no data";
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Dirty_Writeback, desc="The final message as part of a PutX/PutS, contains data";
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2009-08-04 19:52:52 +02:00
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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DMA_READ, desc="DMA Read";
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DMA_WRITE, desc="DMA Write";
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Data, desc="Data to directory";
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2009-05-11 19:38:43 +02:00
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}
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// TYPES
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// DirectoryEntry
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2010-01-30 05:29:26 +01:00
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structure(Entry, desc="...", interface='AbstractEntry') {
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2009-05-11 19:38:43 +02:00
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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int WaitingUnblocks, desc="Number of acks we're waiting for";
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}
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2009-08-04 19:52:52 +02:00
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structure(TBE, desc="...") {
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2009-08-06 10:41:28 +02:00
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Address PhysicalAddress, desc="Physical address for this entry";
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2009-08-04 19:52:52 +02:00
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int Len, desc="Length of request";
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DataBlock DataBlk, desc="DataBlk";
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MachineID Requestor, desc="original requestor";
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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2009-05-11 19:38:43 +02:00
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// ** OBJECTS **
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2009-08-04 19:52:52 +02:00
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TBETable TBEs, template_hack="<Directory_TBE>";
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2009-05-11 19:38:43 +02:00
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Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
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void set_tbe(TBE b);
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void unset_tbe();
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2010-01-30 05:29:26 +01:00
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Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
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return static_cast(Entry, directory[addr]);
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}
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Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
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State getState(TBE tbe, Address addr) {
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2010-01-30 05:29:26 +01:00
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return getDirectoryEntry(addr).DirectoryState;
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2009-05-11 19:38:43 +02:00
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}
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Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
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void setState(TBE tbe, Address addr, State state) {
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2009-05-11 19:38:43 +02:00
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if (directory.isPresent(addr)) {
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if (state == State:I) {
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2010-01-30 05:29:26 +01:00
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assert(getDirectoryEntry(addr).Owner.count() == 0);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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2009-05-11 19:38:43 +02:00
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}
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if (state == State:S) {
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2010-01-30 05:29:26 +01:00
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assert(getDirectoryEntry(addr).Owner.count() == 0);
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2009-05-11 19:38:43 +02:00
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}
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if (state == State:O) {
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2010-01-30 05:29:26 +01:00
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assert(getDirectoryEntry(addr).Owner.count() == 1);
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assert(getDirectoryEntry(addr).Sharers.isSuperset(getDirectoryEntry(addr).Owner) == false);
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2009-05-11 19:38:43 +02:00
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}
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if (state == State:M) {
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2010-01-30 05:29:26 +01:00
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assert(getDirectoryEntry(addr).Owner.count() == 1);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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2009-05-11 19:38:43 +02:00
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}
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if ((state != State:SS) && (state != State:OO)) {
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2010-01-30 05:29:26 +01:00
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assert(getDirectoryEntry(addr).WaitingUnblocks == 0);
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2009-05-11 19:38:43 +02:00
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}
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2010-01-30 05:29:26 +01:00
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if ( (getDirectoryEntry(addr).DirectoryState != State:I) && (state == State:I) ) {
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getDirectoryEntry(addr).DirectoryState := state;
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2009-05-11 19:38:43 +02:00
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// disable coherence checker
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// sequencer.checkCoherence(addr);
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}
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else {
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2010-01-30 05:29:26 +01:00
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getDirectoryEntry(addr).DirectoryState := state;
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2009-05-11 19:38:43 +02:00
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}
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}
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}
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// if no sharers, then directory can be considered both a sharer and exclusive w.r.t. coherence checking
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bool isBlockShared(Address addr) {
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if (directory.isPresent(addr)) {
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2010-01-30 05:29:26 +01:00
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if (getDirectoryEntry(addr).DirectoryState == State:I) {
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2009-05-11 19:38:43 +02:00
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return true;
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}
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}
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return false;
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}
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bool isBlockExclusive(Address addr) {
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if (directory.isPresent(addr)) {
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2010-01-30 05:29:26 +01:00
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if (getDirectoryEntry(addr).DirectoryState == State:I) {
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2009-05-11 19:38:43 +02:00
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return true;
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}
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}
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return false;
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}
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// ** OUT_PORTS **
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out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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// out_port(requestQueue_out, ResponseMsg, requestFromDir); // For recycling requests
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out_port(goo1_out, ResponseMsg, goo1);
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2009-08-04 19:52:52 +02:00
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out_port(memQueue_out, MemoryMsg, memBuffer);
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2009-05-11 19:38:43 +02:00
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// ** IN_PORTS **
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in_port(foo1_in, ResponseMsg, foo1) {
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}
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// in_port(unblockNetwork_in, ResponseMsg, unblockToDir) {
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// if (unblockNetwork_in.isReady()) {
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in_port(unblockNetwork_in, ResponseMsg, responseToDir) {
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if (unblockNetwork_in.isReady()) {
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peek(unblockNetwork_in, ResponseMsg) {
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if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
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2010-01-30 05:29:26 +01:00
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if (getDirectoryEntry(in_msg.Address).WaitingUnblocks == 1) {
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Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Last_Unblock, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Unblock, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
} else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Exclusive_Unblock, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Dirty_Writeback, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceResponseType:WRITEBACK_CLEAN_ACK) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Clean_Writeback, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-08-04 19:52:52 +02:00
|
|
|
} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Data, in_msg.Address,
|
|
|
|
TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else {
|
|
|
|
error("Invalid message");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
in_port(requestQueue_in, RequestMsg, requestToDir) {
|
|
|
|
if (requestQueue_in.isReady()) {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
|
|
|
if (in_msg.Type == CoherenceRequestType:GETS) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:GETS, in_msg.Address, TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:GETX) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:GETX, in_msg.Address, TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:PUTX) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:PUTX, in_msg.Address, TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:PUTO) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:PUTO, in_msg.Address, TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:PUTO_SHARERS, in_msg.Address, TBEs[in_msg.Address]);
|
2009-08-04 19:52:52 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:DMA_READ, makeLineAddress(in_msg.Address),
|
|
|
|
TBEs[makeLineAddress(in_msg.Address)]);
|
2009-08-04 19:52:52 +02:00
|
|
|
} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address),
|
|
|
|
TBEs[makeLineAddress(in_msg.Address)]);
|
2009-08-04 19:52:52 +02:00
|
|
|
} else {
|
|
|
|
error("Invalid message");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// off-chip memory request/response is done
|
|
|
|
in_port(memQueue_in, MemoryMsg, memBuffer) {
|
|
|
|
if (memQueue_in.isReady()) {
|
|
|
|
peek(memQueue_in, MemoryMsg) {
|
|
|
|
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
|
2009-08-04 19:52:52 +02:00
|
|
|
} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
|
2009-05-11 19:38:43 +02:00
|
|
|
} else {
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "%s\n", in_msg.Type);
|
2009-05-11 19:38:43 +02:00
|
|
|
error("Invalid message");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Actions
|
|
|
|
|
|
|
|
action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2009-08-04 19:52:52 +02:00
|
|
|
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := CoherenceRequestType:WB_ACK;
|
|
|
|
out_msg.Requestor := in_msg.Requestor;
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
out_msg.RequestorMachine := MachineType:Directory;
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2009-08-04 19:52:52 +02:00
|
|
|
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := CoherenceRequestType:WB_NACK;
|
|
|
|
out_msg.Requestor := in_msg.Requestor;
|
|
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(c_clearOwner, "c", desc="Clear the owner field") {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).Owner.clear();
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
action(c_moveOwnerToSharer, "cc", desc="Move owner to sharers") {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).Sharers.addNetDest(getDirectoryEntry(address).Owner);
|
|
|
|
getDirectoryEntry(address).Owner.clear();
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
action(cc_clearSharers, "\c", desc="Clear the sharers field") {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).Sharers.clear();
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
action(d_sendDataMsg, "d", desc="Send data to requestor") {
|
|
|
|
peek(memQueue_in, MemoryMsg) {
|
|
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="1") {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.SenderMachine := MachineType:Directory;
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
|
2010-01-30 05:29:26 +01:00
|
|
|
//out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Dirty := false; // By definition, the block is now clean
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.Acks := in_msg.Acks;
|
|
|
|
if (in_msg.ReadX) {
|
|
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
|
|
} else {
|
|
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-11 17:58:37 +02:00
|
|
|
action(p_fwdDataToDMA, "\d", desc="Send data to requestor") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
|
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.SenderMachine := MachineType:Directory;
|
|
|
|
out_msg.Destination.add(in_msg.Requestor);
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
2009-09-11 17:58:37 +02:00
|
|
|
out_msg.Dirty := false; // By definition, the block is now clean
|
|
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
action(e_ownerIsUnblocker, "e", desc="The owner is now the unblocker") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).Owner.clear();
|
|
|
|
getDirectoryEntry(address).Owner.add(in_msg.Sender);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(f_forwardRequest, "f", desc="Forward request to owner") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2009-08-04 19:52:52 +02:00
|
|
|
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := in_msg.Type;
|
|
|
|
out_msg.Requestor := in_msg.Requestor;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
|
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
|
|
|
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Acks := out_msg.Acks - 1;
|
|
|
|
}
|
|
|
|
out_msg.MessageSize := MessageSizeType:Forwarded_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
action(f_forwardRequestDirIsRequestor, "\f", desc="Forward request to owner") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
|
|
|
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := in_msg.Type;
|
|
|
|
out_msg.Requestor := machineID;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
|
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
|
|
|
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.Acks := out_msg.Acks - 1;
|
|
|
|
}
|
|
|
|
out_msg.MessageSize := MessageSizeType:Forwarded_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2010-01-30 05:29:26 +01:00
|
|
|
if ((getDirectoryEntry(in_msg.Address).Sharers.count() > 1) ||
|
|
|
|
((getDirectoryEntry(in_msg.Address).Sharers.count() > 0) && (getDirectoryEntry(in_msg.Address).Sharers.isElement(in_msg.Requestor) == false))) {
|
2009-08-04 19:52:52 +02:00
|
|
|
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := CoherenceRequestType:INV;
|
|
|
|
out_msg.Requestor := in_msg.Requestor;
|
2010-01-30 05:29:26 +01:00
|
|
|
// out_msg.Destination := getDirectoryEntry(in_msg.Address).Sharers;
|
|
|
|
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Sharers);
|
2009-05-11 19:38:43 +02:00
|
|
|
out_msg.Destination.remove(in_msg.Requestor);
|
|
|
|
out_msg.MessageSize := MessageSizeType:Invalidate_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
|
|
|
|
requestQueue_in.dequeue();
|
|
|
|
}
|
|
|
|
|
|
|
|
action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") {
|
|
|
|
unblockNetwork_in.dequeue();
|
|
|
|
}
|
|
|
|
|
|
|
|
action(l_writeDataToMemory, "l", desc="Write PUTX/PUTO data to memory") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
|
|
|
assert(in_msg.Dirty);
|
|
|
|
assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
|
|
|
|
in_msg.Address, in_msg.DataBlk);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-31 23:38:22 +02:00
|
|
|
action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
|
|
|
|
in_msg.Address, in_msg.DataBlk);
|
2009-08-31 23:38:22 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
action(ll_checkDataInMemory, "\ld", desc="Check PUTX/PUTO data is same as in the memory") {
|
2009-05-11 19:38:43 +02:00
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
|
|
|
assert(in_msg.Dirty == false);
|
|
|
|
assert(in_msg.MessageSize == MessageSizeType:Writeback_Control);
|
|
|
|
|
|
|
|
// NOTE: The following check would not be valid in a real
|
|
|
|
// implementation. We include the data in the "dataless"
|
|
|
|
// message so we can assert the clean data matches the datablock
|
|
|
|
// in memory
|
2010-01-30 05:29:26 +01:00
|
|
|
assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(m_addUnlockerToSharers, "m", desc="Add the unlocker to the sharer list") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).Sharers.add(in_msg.Sender);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(n_incrementOutstanding, "n", desc="Increment outstanding requests") {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks + 1;
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
action(o_decrementOutstanding, "o", desc="Decrement outstanding requests") {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks - 1;
|
|
|
|
assert(getDirectoryEntry(address).WaitingUnblocks >= 0);
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
action(q_popMemQueue, "q", desc="Pop off-chip request queue") {
|
|
|
|
memQueue_in.dequeue();
|
|
|
|
}
|
|
|
|
|
|
|
|
action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
|
|
|
enqueue(memQueue_out, MemoryMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := MemoryRequestType:MEMORY_READ;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
|
|
//out_msg.Prefetch := false;
|
|
|
|
// These are not used by memory but are passed back here with the read data:
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && getDirectoryEntry(address).Sharers.count() == 0);
|
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
|
|
|
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.Acks := out_msg.Acks - 1;
|
|
|
|
}
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
|
|
|
enqueue(memQueue_out, MemoryMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
|
|
out_msg.Sender := machineID;
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
if (is_valid(tbe)) {
|
|
|
|
out_msg.OriginalRequestorMachId := tbe.Requestor;
|
|
|
|
}
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
|
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
|
|
//out_msg.Prefetch := false;
|
|
|
|
// Not used:
|
|
|
|
out_msg.ReadX := false;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(qw_queueMemoryWBRequest2, "/qw", desc="Queue off-chip writeback request") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
|
|
|
enqueue(memQueue_out, MemoryMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
|
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
|
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
|
|
//out_msg.Prefetch := false;
|
|
|
|
// Not used:
|
|
|
|
out_msg.ReadX := false;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
2010-12-01 20:30:04 +01:00
|
|
|
DPRINTF(RubySlicc, "%s\n", out_msg);
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
// action(z_stall, "z", desc="Cannot be handled right now.") {
|
|
|
|
// Special name recognized as do nothing case
|
|
|
|
// }
|
|
|
|
|
|
|
|
action(zz_recycleRequest, "\z", desc="Recycle the request queue") {
|
|
|
|
requestQueue_in.recycle();
|
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along with Inv Ack count") {
|
2009-08-31 23:38:22 +02:00
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2009-08-04 19:52:52 +02:00
|
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.SenderMachine := MachineType:Directory;
|
2009-08-31 23:38:22 +02:00
|
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
2009-08-31 23:38:22 +02:00
|
|
|
out_msg.Type := CoherenceResponseType:DMA_ACK;
|
|
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(a_sendDMAAck2, "\aa", desc="Send DMA Ack that write completed, along with Inv Ack count") {
|
|
|
|
peek(unblockNetwork_in, ResponseMsg) {
|
|
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="1") {
|
|
|
|
out_msg.Address := address;
|
|
|
|
out_msg.Sender := machineID;
|
|
|
|
out_msg.SenderMachine := MachineType:Directory;
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
if (is_valid(tbe)) {
|
|
|
|
out_msg.Destination.add(tbe.Requestor);
|
2009-08-31 23:38:22 +02:00
|
|
|
}
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
2010-01-30 05:29:26 +01:00
|
|
|
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
2009-08-04 19:52:52 +02:00
|
|
|
out_msg.Type := CoherenceResponseType:DMA_ACK;
|
|
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(l_writeDMADataToMemory, "\l", desc="Write data from a DMA_WRITE to memory") {
|
|
|
|
peek(requestQueue_in, RequestMsg) {
|
2010-01-30 05:29:26 +01:00
|
|
|
getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") {
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
assert(is_valid(tbe));
|
|
|
|
getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk,
|
|
|
|
addressOffset(tbe.PhysicalAddress), tbe.Len);
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
|
|
|
|
peek (requestQueue_in, RequestMsg) {
|
|
|
|
TBEs.allocate(address);
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
set_tbe(TBEs[address]);
|
|
|
|
tbe.PhysicalAddress := in_msg.Address;
|
|
|
|
tbe.Len := in_msg.Len;
|
|
|
|
tbe.DataBlk := in_msg.DataBlk;
|
|
|
|
tbe.Requestor := in_msg.Requestor;
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
|
|
|
|
TBEs.deallocate(address);
|
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
2011-01-18 01:46:16 +01:00
|
|
|
unset_tbe();
|
2009-08-04 19:52:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
// TRANSITIONS
|
|
|
|
|
|
|
|
transition(I, GETX, MM) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qf_queueMemoryFetchRequest;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(I, DMA_READ, XI_M) {
|
|
|
|
qf_queueMemoryFetchRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-31 23:38:22 +02:00
|
|
|
transition(I, DMA_WRITE, XI_U) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest2;
|
2009-08-31 23:38:22 +02:00
|
|
|
a_sendDMAAck; // ack count may be zero
|
2009-08-04 19:52:52 +02:00
|
|
|
l_writeDMADataToMemory;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-09-11 17:58:37 +02:00
|
|
|
transition(XI_M, Memory_Data, I) {
|
2009-08-04 19:52:52 +02:00
|
|
|
d_sendDataMsg; // ack count may be zero
|
|
|
|
q_popMemQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(XI_U, Exclusive_Unblock, I) {
|
|
|
|
cc_clearSharers;
|
|
|
|
c_clearOwner;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
transition(S, GETX, MM) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qf_queueMemoryFetchRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
g_sendInvalidations;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-09-11 17:58:37 +02:00
|
|
|
transition(S, DMA_READ, S) {
|
|
|
|
//qf_queueMemoryFetchRequest;
|
|
|
|
p_fwdDataToDMA;
|
|
|
|
//g_sendInvalidations; // the DMA will collect the invalidations then send an Unblock Exclusive
|
2009-08-04 19:52:52 +02:00
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-31 23:38:22 +02:00
|
|
|
transition(S, DMA_WRITE, XI_U) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest2;
|
2009-08-31 23:38:22 +02:00
|
|
|
a_sendDMAAck; // ack count may be zero
|
2009-08-04 19:52:52 +02:00
|
|
|
l_writeDMADataToMemory;
|
|
|
|
g_sendInvalidations; // the DMA will collect invalidations
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
transition(I, GETS, IS) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qf_queueMemoryFetchRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({S, SS}, GETS, SS) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qf_queueMemoryFetchRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
n_incrementOutstanding;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({I, S}, PUTO) {
|
|
|
|
b_sendWriteBackNack;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({I, S, O}, PUTX) {
|
|
|
|
b_sendWriteBackNack;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(O, GETX, MM) {
|
|
|
|
f_forwardRequest;
|
|
|
|
g_sendInvalidations;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-09-11 17:58:37 +02:00
|
|
|
transition(O, DMA_READ, O) {
|
2009-08-04 19:52:52 +02:00
|
|
|
f_forwardRequest; // this will cause the data to go to DMA directly
|
2009-09-11 17:58:37 +02:00
|
|
|
//g_sendInvalidations; // this will cause acks to be sent to the DMA
|
2009-08-04 19:52:52 +02:00
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({O,M}, DMA_WRITE, OI_D) {
|
|
|
|
f_forwardRequestDirIsRequestor; // need the modified data before we can proceed
|
|
|
|
g_sendInvalidations; // these go to the DMA Controller
|
|
|
|
v_allocateTBE;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-31 23:38:22 +02:00
|
|
|
transition(OI_D, Data, XI_U) {
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest;
|
2009-08-31 23:38:22 +02:00
|
|
|
a_sendDMAAck2; // ack count may be zero
|
|
|
|
p_writeFwdDataToMemory;
|
2009-08-04 19:52:52 +02:00
|
|
|
l_writeDMADataToMemoryFromTBE;
|
|
|
|
w_deallocateTBE;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
transition({O, OO}, GETS, OO) {
|
|
|
|
f_forwardRequest;
|
|
|
|
n_incrementOutstanding;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(M, GETX, MM) {
|
|
|
|
f_forwardRequest;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-04 19:52:52 +02:00
|
|
|
// no exclusive unblock will show up to the directory
|
2009-09-11 17:58:37 +02:00
|
|
|
transition(M, DMA_READ, M) {
|
2009-08-04 19:52:52 +02:00
|
|
|
f_forwardRequest; // this will cause the data to go to DMA directly
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
transition(M, GETS, MO) {
|
|
|
|
f_forwardRequest;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(M, PUTX, MI) {
|
|
|
|
a_sendWriteBackAck;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// happens if M->O transition happens on-chip
|
|
|
|
transition(M, PUTO, MI) {
|
|
|
|
a_sendWriteBackAck;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(M, PUTO_SHARERS, MIS) {
|
|
|
|
a_sendWriteBackAck;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(O, PUTO, OS) {
|
|
|
|
a_sendWriteBackAck;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(O, PUTO_SHARERS, OSS) {
|
|
|
|
a_sendWriteBackAck;
|
|
|
|
i_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-08-09 20:58:40 +02:00
|
|
|
transition({MM, MO, MI, MIS, OS, OSS, XI_M, XI_U, OI_D}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) {
|
2009-05-11 19:38:43 +02:00
|
|
|
zz_recycleRequest;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({MM, MO}, Exclusive_Unblock, M) {
|
|
|
|
cc_clearSharers;
|
|
|
|
e_ownerIsUnblocker;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(MO, Unblock, O) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-09 20:58:40 +02:00
|
|
|
transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) {
|
2009-05-11 19:38:43 +02:00
|
|
|
zz_recycleRequest;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(IS, GETS) {
|
|
|
|
zz_recycleRequest;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(IS, Unblock, S) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(IS, Exclusive_Unblock, M) {
|
|
|
|
cc_clearSharers;
|
|
|
|
e_ownerIsUnblocker;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(SS, Unblock) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
o_decrementOutstanding;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(SS, Last_Unblock, S) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
o_decrementOutstanding;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OO, Unblock) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
o_decrementOutstanding;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OO, Last_Unblock, O) {
|
|
|
|
m_addUnlockerToSharers;
|
|
|
|
o_decrementOutstanding;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(MI, Dirty_Writeback, I) {
|
|
|
|
c_clearOwner;
|
|
|
|
cc_clearSharers;
|
|
|
|
l_writeDataToMemory;
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(MIS, Dirty_Writeback, S) {
|
|
|
|
c_moveOwnerToSharer;
|
|
|
|
l_writeDataToMemory;
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(MIS, Clean_Writeback, S) {
|
|
|
|
c_moveOwnerToSharer;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OS, Dirty_Writeback, S) {
|
|
|
|
c_clearOwner;
|
|
|
|
l_writeDataToMemory;
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OSS, Dirty_Writeback, S) {
|
|
|
|
c_moveOwnerToSharer;
|
|
|
|
l_writeDataToMemory;
|
2009-08-04 19:52:52 +02:00
|
|
|
qw_queueMemoryWBRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OSS, Clean_Writeback, S) {
|
|
|
|
c_moveOwnerToSharer;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(MI, Clean_Writeback, I) {
|
|
|
|
c_clearOwner;
|
|
|
|
cc_clearSharers;
|
|
|
|
ll_checkDataInMemory;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(OS, Clean_Writeback, S) {
|
|
|
|
c_clearOwner;
|
|
|
|
ll_checkDataInMemory;
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({MI, MIS}, Unblock, M) {
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({OS, OSS}, Unblock, O) {
|
|
|
|
j_popIncomingUnblockQueue;
|
|
|
|
}
|
2009-08-04 19:52:52 +02:00
|
|
|
|
|
|
|
transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data) {
|
|
|
|
d_sendDataMsg;
|
|
|
|
q_popMemQueue;
|
|
|
|
}
|
|
|
|
|
2009-08-31 23:38:22 +02:00
|
|
|
transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS, XI_U, XI_M}, Memory_Ack) {
|
2009-08-04 19:52:52 +02:00
|
|
|
//a_sendAck;
|
|
|
|
q_popMemQueue;
|
|
|
|
}
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|