gem5/src/arch/arm/isa/bitfields.isa

// -*- mode:c++ -*-

// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
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// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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//
// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

// Opcode fields
def bitfield ENCODING      encoding;
def bitfield OPCODE        opcode;
def bitfield MEDIA_OPCODE  mediaOpcode;
def bitfield MEDIA_OPCODE2 mediaOpcode2;
def bitfield USEIMM        useImm;
def bitfield OPCODE_24	   opcode24;
def bitfield OPCODE_23_20  opcode23_20;
def bitfield OPCODE_23_21  opcode23_21;
def bitfield OPCODE_22     opcode22;
def bitfield OPCODE_20	   opcode20;
def bitfield OPCODE_19	   opcode19;
def bitfield OPCODE_18	   opcode18;
def bitfield OPCODE_15_12  opcode15_12;
def bitfield OPCODE_15	   opcode15;
def bitfield MISC_OPCODE   miscOpcode;
def bitfield OPC2          opc2; 
def bitfield OPCODE_7      opcode7;
def bitfield OPCODE_4      opcode4;

def bitfield IS_MISC       isMisc;
def bitfield SEVEN_AND_FOUR sevenAndFour;

// Other
def bitfield COND_CODE     condCode;
def bitfield S_FIELD       sField;
def bitfield RN            rn;
def bitfield RD            rd;
def bitfield SHIFT_SIZE    shiftSize;
def bitfield SHIFT         shift;
def bitfield RM            rm;

def bitfield RS            rs;

def bitfield PUSWL         puswl;
def bitfield PREPOST       puswl.prepost;
def bitfield UP               puswl.up;
def bitfield PSRUSER       puswl.psruser;
def bitfield WRITEBACK     puswl.writeback;
def bitfield LOADOP        puswl.loadOp;

def bitfield PUBWL         pubwl;

def bitfield IMM           imm;

def bitfield IMMED_11_0    immed11_0;

def bitfield IMMED_HI_11_8 immedHi11_8;
def bitfield IMMED_LO_3_0  immedLo3_0;

def bitfield IMMED_23_0    immed23_0;

def bitfield CPNUM	   cpNum;
// Note that FP Regs are only 3 bits
def bitfield FN		   fn;
def bitfield FD		   fd;
def bitfield FPREGIMM	   fpRegImm;
// We can just use 3:0 for FM since the hard-wired FP regs are handled in
// float_regfile.hh
def bitfield FM		   fm;
def bitfield FPIMM	   fpImm;
def bitfield PUNWL	   punwl;

// M5 instructions
def bitfield M5FUNC        m5Func;