gem5/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                  54292                       # Simulator instruction rate (inst/s)
host_mem_usage                                 158040                       # Number of bytes of host memory used
host_seconds                                  1692.76                       # Real time elapsed on the host
host_tick_rate                               58297931                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    91903056                       # Number of instructions simulated
sim_seconds                                  0.098684                       # Number of seconds simulated
sim_ticks                                 98684146000                       # Number of ticks simulated
system.cpu.AGEN-Unit.agens                   26537108                       # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct       63.856280                       # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits           5483107                       # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups        8586637                       # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect      1029596                       # Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect      3205078                       # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted      7465012                       # Number of conditional branches predicted
system.cpu.Branch-Predictor.lookups          10240685                       # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken      2715877                       # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken      7524808                       # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS           1029596                       # Number of times the RAS was used to get a target.
system.cpu.Execution-Unit.executions         64907696                       # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct     31.297496                       # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted        3205078                       # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted           7035607                       # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predictedNotTakenIncorrect       357110                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect      2847968                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies            458252                       # Number of Multipy Operations Executed
system.cpu.RegFile-Manager.regFileAccesses    185972249                       # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads     117544888                       # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites     68427361                       # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards        2843109                       # Number of Registers Read Through Forwarding Logic
system.cpu.activity                         95.924038                       # Percentage of cycles cpu is active
system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
system.cpu.comInts                           43625545                       # Number of Integer instructions committed
system.cpu.comLoads                          20034413                       # Number of Load instructions committed
system.cpu.comNonSpec                             389                       # Number of Non-Speculative instructions committed
system.cpu.comNops                            7723346                       # Number of Nop instructions committed
system.cpu.comStores                          6502695                       # Number of Store instructions committed
system.cpu.committedInsts                    91903056                       # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total              91903056                       # Number of Instructions Simulated (Total)
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.cpi                               2.147571                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total                         2.147571                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 51585.263158                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48561.052632                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               19995723                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency       24503000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                  475                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency     23066500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56218.934911                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53218.934911                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits               6499244                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency     104511000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.000286                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                1859                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency     98934000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000286                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses           1859                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55275.921165                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52270.994002                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                26494967                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       129014000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000088                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                  2334                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency    122000500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000088                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses             2334                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.352002                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           1441.798330                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55275.921165                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52270.994002                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               26494967                       # number of overall hits
system.cpu.dcache.overall_miss_latency      129014000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000088                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                 2334                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency    122000500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000088                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses            2334                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                    157                       # number of replacements
system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               1441.798330                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                      104                       # number of writebacks
system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_hits                     26497301                       # DTB hits
system.cpu.dtb.data_misses                         33                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                     19996198                       # DTB read hits
system.cpu.dtb.read_misses                         10                       # DTB read misses
system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                     6501103                       # DTB write hits
system.cpu.dtb.write_misses                        23                       # DTB write misses
system.cpu.icache.ReadReq_accesses          102632944                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 27261.770785                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23983.385799                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              102624236                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      237395500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000085                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 8708                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               131                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    205705500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000084                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            8577                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets         2500                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               11965.050251                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets         2500                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           102632944                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 27261.770785                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23983.385799                       # average overall mshr miss latency
system.cpu.icache.demand_hits               102624236                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       237395500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000085                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  8708                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                131                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    205705500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             8577                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.697567                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0           1428.616252                       # Average occupied blocks per context
system.cpu.icache.overall_accesses          102632944                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 27261.770785                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23983.385799                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              102624236                       # number of overall hits
system.cpu.icache.overall_miss_latency      237395500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000085                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 8708                       # number of overall misses
system.cpu.icache.overall_mshr_hits               131                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    205705500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            8577                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                   6743                       # number of replacements
system.cpu.icache.sampled_refs                   8577                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1428.616252                       # Cycle average of tags in use
system.cpu.icache.total_refs                102624236                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                         8044656                       # Number of cycles cpu's stages were not processed
system.cpu.ipc                               0.465642                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total                         0.465642                       # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses               102632992                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                   102632945                       # ITB hits
system.cpu.itb.fetch_misses                        47                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52211.384439                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency     91265500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses              1748                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency     69930000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses         1748                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses              9052                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52168.952008                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40019.915116                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                  5989                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency     159793500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.338378                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                3063                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency    122581000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338378                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses           3063                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses            111                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52274.774775                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency      5802500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses              111                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency      4441000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses          111                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  1.971947                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses              10800                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52184.369154                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.757847                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                   5989                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency      251059000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.445463                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                 4811                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency    192511000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.445463                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses            4811                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.061818                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.000419                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0          2025.652199                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1            13.726445                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses             10800                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52184.369154                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.757847                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                  5989                       # number of overall hits
system.cpu.l2cache.overall_miss_latency     251059000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.445463                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                4811                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency    192511000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.445463                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses           4811                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                  3030                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse              2039.378644                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    5975                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                        197368293                       # number of cpu cycles simulated
system.cpu.runCycles                        189323637                       # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
system.cpu.stage-0.idleCycles                94735301                       # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles                102632992                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-0.utilization              52.000750                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles               105250860                       # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles                 92117433                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization              46.672863                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles               103875809                       # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles                 93492484                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization              47.369556                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles               170831162                       # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles                 26537131                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization              13.445488                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles               105465237                       # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles                 91903056                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization              46.564245                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles                     197368293                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls

---------- End Simulation Statistics   ----------