2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2012-07-27 22:08:05 +02:00
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sim_seconds 0.213306 # Number of seconds simulated
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sim_ticks 213305827500 # Number of ticks simulated
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final_tick 213305827500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-07-27 22:08:05 +02:00
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host_inst_rate 122434 # Simulator instruction rate (inst/s)
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host_op_rate 137922 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 51312604 # Simulator tick rate (ticks/s)
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host_mem_usage 243816 # Number of bytes of host memory used
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host_seconds 4156.99 # Real time elapsed on the host
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2012-07-09 18:35:41 +02:00
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sim_insts 508955143 # Number of instructions simulated
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sim_ops 573341703 # Number of ops (including micro ops) simulated
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2012-07-27 22:08:05 +02:00
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system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10018112 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10236992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6680832 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6680832 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 156533 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 159953 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 104388 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 104388 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1026132 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 46965955 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 47992088 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1026132 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1026132 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 31320438 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 31320438 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 31320438 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1026132 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 46965955 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 79312526 # Total bandwidth to/from this memory (bytes/s)
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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2012-07-27 22:08:05 +02:00
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system.cpu.numCycles 426611656 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-07-27 22:08:05 +02:00
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system.cpu.BPredUnit.lookups 180727823 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 143302439 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 7746795 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 94842136 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 87606401 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-07-27 22:08:05 +02:00
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system.cpu.BPredUnit.usedRAS 12449624 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 117248 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 121010673 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 797304667 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 180727823 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 100056025 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 177314401 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 41698826 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 95806477 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 633 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 114358410 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 2503764 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 425037502 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.155810 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.022430 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2012-07-27 22:08:05 +02:00
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system.cpu.fetch.rateDist::0 247735901 58.29% 58.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 14398989 3.39% 61.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 20690991 4.87% 66.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 22948184 5.40% 71.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 21028166 4.95% 76.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 13190111 3.10% 79.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 13289231 3.13% 83.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 12171348 2.86% 85.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 59584581 14.02% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-07-27 22:08:05 +02:00
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system.cpu.fetch.rateDist::total 425037502 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.423635 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.868924 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 133844968 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 89919956 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 165224759 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 5218013 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 30829806 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 26552808 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 78494 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 873544954 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 311862 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 30829806 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 144308291 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 8889002 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 66226963 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 159805436 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 14978004 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 818752285 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 1493 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 2838539 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 8233022 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 166 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 966651195 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 3575004515 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 3574999805 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 4710 # Number of floating rename lookups
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2012-07-09 18:35:41 +02:00
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system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed
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2012-07-27 22:08:05 +02:00
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system.cpu.rename.UndoneMaps 294451032 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 5324262 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 5323899 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 70506892 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 172716678 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 75192368 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 27652992 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 15476560 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 763674623 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 6775753 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 672581286 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1543643 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 194823037 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 494499430 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 3054637 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 425037502 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.582405 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.714766 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2012-07-27 22:08:05 +02:00
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system.cpu.iq.issued_per_cycle::0 161217436 37.93% 37.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 79193919 18.63% 56.56% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 71219740 16.76% 73.32% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 52703176 12.40% 85.72% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 30630317 7.21% 92.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 16016984 3.77% 96.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 9411904 2.21% 98.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3391461 0.80% 99.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1252565 0.29% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2012-07-27 22:08:05 +02:00
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system.cpu.iq.issued_per_cycle::total 425037502 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-07-27 22:08:05 +02:00
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system.cpu.iq.fu_full::IntAlu 468985 4.81% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available
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|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 6682386 68.55% 73.36% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 2596899 26.64% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 451788730 67.17% 67.17% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 385834 0.06% 67.23% # Type of FU issued
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 242 0.00% 67.23% # Type of FU issued
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 155276883 23.09% 90.32% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 65129594 9.68% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 672581286 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.576566 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 9748270 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 1781491468 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 966076983 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 652193699 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 519 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 994 # Number of floating instruction queue writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 682329295 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 261 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 8459367 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 45943639 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 43480 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 808541 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 17588407 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 19485 # Number of loads that were rescheduled
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1190 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 30829806 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 4164559 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 269371 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 776620659 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1214502 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 172716678 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 75192368 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 5287034 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 138183 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 8014 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 808541 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4710218 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 6437306 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 11147524 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 662618807 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 151738432 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 9962479 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iew.exec_nop 6170283 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 215459970 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 137327241 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 63721538 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.553213 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 657384625 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 652193715 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 375712620 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 644546393 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.iew.wb_rate 1.528776 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.582910 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 201955385 # The number of squashed insts skipped by commit
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.commit.branchMispredicts 9921280 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 394207697 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.457824 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.150931 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 179674322 45.58% 45.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 103038794 26.14% 71.72% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 36295508 9.21% 80.92% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 18900800 4.79% 85.72% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 16480626 4.18% 89.90% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 8181222 2.08% 91.97% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 6907237 1.75% 93.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3752163 0.95% 94.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 20977025 5.32% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 394207697 # Number of insts commited each cycle
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.committedInsts 510299027 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.refs 184377000 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 126773039 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.branches 120192224 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.commit.int_insts 473701629 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.commit.bw_lim_events 20977025 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.rob.rob_reads 1149864506 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1584255068 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 77013 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 1574154 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.committedInsts 508955143 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.cpi 0.838211 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.838211 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.193017 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.193017 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3092210365 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 760501959 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.misc_regfile_reads 1025217817 # number of misc regfile reads
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.replacements 15942 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1098.022149 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 114338741 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 17803 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 6422.442341 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 1098.022149 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.536144 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.536144 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 114338741 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 114338741 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 114338741 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 114338741 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 114338741 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 114338741 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 19669 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 19669 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 19669 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 19669 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 19669 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 19669 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 281943000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 281943000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 281943000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 281943000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 281943000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 281943000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 114358410 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 114358410 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 114358410 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 114358410 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 114358410 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 114358410 # number of overall (read+write) accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000172 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000172 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000172 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000172 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000172 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000172 # miss rate for overall accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14334.384056 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14334.384056 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 14334.384056 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 14334.384056 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1810 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1810 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1810 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 1810 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1810 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 1810 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17859 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 17859 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 17859 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 17859 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 17859 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 17859 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184851000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 184851000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184851000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 184851000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184851000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 184851000 # number of overall MSHR miss cycles
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000156 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000156 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000156 # mshr miss rate for overall accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10350.579540 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10350.579540 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.replacements 1188372 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4054.528843 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 194724251 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1192468 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 163.295158 # Average number of references to valid blocks.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 4858281000 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4054.528843 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.989875 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.989875 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 137575577 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 137575577 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 52683646 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 52683646 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232872 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 2232872 # number of LoadLockedReq hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 2232025 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 2232025 # number of StoreCondReq hits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 190259223 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 190259223 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 190259223 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 190259223 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1266823 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1266823 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1555660 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1555660 # number of WriteReq misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 2822483 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 2822483 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 2822483 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 2822483 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15537538000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 15537538000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33101884500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 33101884500 # number of WriteReq miss cycles
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 516500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 516500 # number of LoadLockedReq miss cycles
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 48639422500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 48639422500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 48639422500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 48639422500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 138842400 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 138842400 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232913 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 2232913 # number of LoadLockedReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses)
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 193081706 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 193081706 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 193081706 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 193081706 # number of overall (read+write) accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009124 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.009124 # miss rate for ReadReq accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028681 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.028681 # miss rate for WriteReq accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.014618 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.014618 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.014618 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.014618 # miss rate for overall accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12264.963614 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 12264.963614 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.354203 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.354203 # average WriteReq miss latency
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 17232.848701 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 17232.848701 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 3299000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 5901.610018 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 1102743 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1102743 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422432 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 422432 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1207529 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1207529 # number of WriteReq MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1629961 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 1629961 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1629961 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 1629961 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844391 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 844391 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348131 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 348131 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1192522 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1192522 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1192522 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1192522 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793957000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793957000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284082001 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284082001 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9078039001 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9078039001 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9078039001 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9078039001 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006082 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006176 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006176 # mshr miss rate for overall accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5677.413663 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5677.413663 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.948051 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.948051 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7612.470882 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7612.470882 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7612.470882 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7612.470882 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.replacements 128760 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26550.688656 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1724027 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 159983 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 10.776314 # Average number of references to valid blocks.
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 109550112000 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 22719.838493 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 309.354854 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 3521.495310 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.693354 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.009441 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.107468 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.810263 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14376 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 787309 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 801685 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1102743 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1102743 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 248604 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 248604 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14376 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1035913 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 1050289 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14376 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1035913 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 1050289 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3427 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53062 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 56489 # number of ReadReq misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 103493 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 103493 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3427 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 156555 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 159982 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3427 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 156555 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 159982 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121113500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1832817500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1953931000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3547748000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3547748000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 121113500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 5380565500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 5501679000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 121113500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 5380565500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 5501679000 # number of overall miss cycles
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 17803 # number of ReadReq accesses(hits+misses)
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 840371 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 858174 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1102743 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1102743 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 54 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 54 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 352097 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 352097 # number of ReadExReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 17803 # number of demand (read+write) accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1192468 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 1210271 # number of demand (read+write) accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 17803 # number of overall (read+write) accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1192468 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 1210271 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192496 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.063141 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.065825 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.111111 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.111111 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.293933 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.293933 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192496 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.131287 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.132187 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192496 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.131287 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.132187 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35340.968777 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34541.055746 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34589.583813 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34280.076913 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34280.076913 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35340.968777 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34368.531826 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34389.362553 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35340.968777 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34368.531826 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34389.362553 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 104388 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 104388 # number of writebacks
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3420 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53041 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 56461 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103493 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 103493 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 156534 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 159954 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 156534 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 159954 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110207000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665041000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775248000 # number of ReadReq MSHR miss cycles
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186000 # number of UpgradeReq MSHR miss cycles
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3213249000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3213249000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110207000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4878290000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 4988497000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110207000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4878290000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 4988497000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063116 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065792 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293933 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293933 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.132164 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.132164 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32224.269006 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31391.583869 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31442.021927 # average ReadReq mshr miss latency
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.983922 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.983922 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
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|
---------- End Simulation Statistics ----------
|
