2006-06-28 17:02:14 +02:00
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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2007-05-19 07:35:04 +02:00
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* Steve Reinhardt
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* Ron Dreslinski
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2006-06-28 17:02:14 +02:00
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*/
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/**
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* @file
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* Declares a basic cache interface BaseCache.
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*/
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#ifndef __BASE_CACHE_HH__
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#define __BASE_CACHE_HH__
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#include <vector>
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#include <string>
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#include <list>
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2007-06-25 15:47:05 +02:00
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#include <algorithm>
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2006-06-28 17:02:14 +02:00
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2006-06-30 17:34:27 +02:00
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#include "base/misc.hh"
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2006-06-28 17:02:14 +02:00
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#include "base/statistics.hh"
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#include "base/trace.hh"
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2009-05-17 23:34:51 +02:00
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#include "base/types.hh"
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2010-02-23 18:34:22 +01:00
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#include "config/full_system.hh"
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2008-02-10 23:45:25 +01:00
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#include "mem/cache/mshr_queue.hh"
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2006-06-28 17:02:14 +02:00
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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2007-06-18 02:27:53 +02:00
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#include "mem/tport.hh"
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2006-06-28 17:02:14 +02:00
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#include "mem/request.hh"
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2007-08-30 21:16:59 +02:00
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#include "params/BaseCache.hh"
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2006-06-28 20:35:00 +02:00
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#include "sim/eventq.hh"
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2007-06-18 02:27:53 +02:00
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#include "sim/sim_exit.hh"
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2006-06-28 17:02:14 +02:00
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2006-10-09 22:37:02 +02:00
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class MSHR;
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2006-06-28 17:02:14 +02:00
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/**
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* A basic cache interface. Implements some common functions for speed.
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*/
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class BaseCache : public MemObject
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{
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2007-06-21 20:59:17 +02:00
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/**
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* Indexes to enumerate the MSHR queues.
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*/
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enum MSHRQueueIndex {
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MSHRQueue_MSHRs,
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MSHRQueue_WriteBuffer
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};
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/**
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* Reasons for caches to be blocked.
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*/
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enum BlockedCause {
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Blocked_NoMSHRs = MSHRQueue_MSHRs,
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Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
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Blocked_NoTargets,
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NUM_BLOCKED_CAUSES
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};
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public:
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/**
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* Reasons for cache to request a bus.
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*/
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enum RequestCause {
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Request_MSHR = MSHRQueue_MSHRs,
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Request_WB = MSHRQueue_WriteBuffer,
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Request_PF,
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NUM_REQUEST_CAUSES
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};
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private:
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2007-06-18 02:27:53 +02:00
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class CachePort : public SimpleTimingPort
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2006-06-28 17:02:14 +02:00
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{
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2006-07-06 21:15:37 +02:00
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public:
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2006-06-28 17:02:14 +02:00
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BaseCache *cache;
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2006-06-28 20:35:00 +02:00
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protected:
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2007-08-10 22:14:01 +02:00
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CachePort(const std::string &_name, BaseCache *_cache,
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2008-07-16 20:10:33 +02:00
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const std::string &_label);
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2007-05-19 07:35:04 +02:00
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2006-06-28 17:02:14 +02:00
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virtual void recvStatusChange(Status status);
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2009-06-05 08:21:12 +02:00
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virtual unsigned deviceBlockSize() const;
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2006-06-28 17:02:14 +02:00
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2007-05-19 07:35:04 +02:00
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bool recvRetryCommon();
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2006-08-16 21:54:02 +02:00
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2007-06-25 15:47:05 +02:00
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typedef EventWrapper<Port, &Port::sendRetry>
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SendRetryEvent;
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2008-01-02 21:20:15 +01:00
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const std::string label;
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2006-06-28 20:35:00 +02:00
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public:
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2007-05-19 07:35:04 +02:00
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void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
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2006-06-28 17:02:14 +02:00
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void setBlocked();
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void clearBlocked();
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2008-01-02 21:20:15 +01:00
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bool checkFunctional(PacketPtr pkt);
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2006-11-11 04:45:50 +01:00
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2007-05-19 07:35:04 +02:00
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CachePort *otherPort;
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2006-06-28 17:02:14 +02:00
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bool blocked;
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2007-06-18 02:27:53 +02:00
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bool mustSendRetry;
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2007-05-19 07:35:04 +02:00
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void requestBus(RequestCause cause, Tick time)
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{
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2007-07-14 22:16:58 +02:00
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DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
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2007-06-25 15:47:05 +02:00
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if (!waitingOnRetry) {
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schedSendEvent(time);
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2007-05-19 07:35:04 +02:00
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}
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}
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2007-05-14 07:58:06 +02:00
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2007-06-18 02:27:53 +02:00
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void respond(PacketPtr pkt, Tick time) {
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schedSendTiming(pkt, time);
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}
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2006-06-28 20:35:00 +02:00
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};
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2006-06-28 17:02:14 +02:00
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2006-10-20 02:02:57 +02:00
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public: //Made public so coherence can get at it.
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2006-06-28 17:02:14 +02:00
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CachePort *cpuSidePort;
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2006-12-14 07:04:36 +01:00
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CachePort *memSidePort;
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2006-10-20 02:02:57 +02:00
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2007-06-18 02:27:53 +02:00
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protected:
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/** Miss status registers */
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MSHRQueue mshrQueue;
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/** Write/writeback buffer */
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MSHRQueue writeBuffer;
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2007-06-21 20:59:17 +02:00
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MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
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PacketPtr pkt, Tick time, bool requestBus)
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{
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2007-06-25 15:47:05 +02:00
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MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
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2007-06-21 20:59:17 +02:00
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if (mq->isFull()) {
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setBlocked((BlockedCause)mq->index);
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}
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if (requestBus) {
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requestMemSideBus((RequestCause)mq->index, time);
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}
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return mshr;
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}
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void markInServiceInternal(MSHR *mshr)
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{
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MSHRQueue *mq = mshr->queue;
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bool wasFull = mq->isFull();
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mq->markInService(mshr);
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if (wasFull && !mq->isFull()) {
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clearBlocked((BlockedCause)mq->index);
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}
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}
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2007-06-18 02:27:53 +02:00
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/** Block size of this cache */
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2009-06-05 08:21:12 +02:00
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const unsigned blkSize;
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2007-06-18 02:27:53 +02:00
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2007-06-22 18:24:07 +02:00
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/**
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* The latency of a hit in this device.
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*/
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int hitLatency;
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2007-06-18 02:27:53 +02:00
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/** The number of targets for each MSHR. */
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const int numTarget;
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2008-07-16 20:10:33 +02:00
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/** Do we forward snoops from mem side port through to cpu side port? */
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bool forwardSnoops;
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2007-06-18 02:27:53 +02:00
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2006-06-28 17:02:14 +02:00
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/**
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* Bit vector of the blocking reasons for the access path.
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* @sa #BlockedCause
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*/
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uint8_t blocked;
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2008-07-16 20:10:33 +02:00
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/** Increasing order number assigned to each incoming request. */
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uint64_t order;
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2006-06-28 17:02:14 +02:00
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/** Stores time the cache blocked for statistics. */
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Tick blockedCycle;
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2007-06-18 02:27:53 +02:00
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/** Pointer to the MSHR that has no targets. */
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MSHR *noTargetMSHR;
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2006-06-28 17:02:14 +02:00
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/** The number of misses to trigger an exit event. */
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Counter missCount;
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2006-11-07 20:25:54 +01:00
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/** The drain event. */
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Event *drainEvent;
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2008-07-16 20:10:33 +02:00
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/**
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* The address range to which the cache responds on the CPU side.
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* Normally this is all possible memory addresses. */
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Range<Addr> addrRange;
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2010-02-23 18:34:22 +01:00
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/** number of cpus sharing this cache - from config file */
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int _numCpus;
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2006-06-28 17:02:14 +02:00
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public:
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2010-02-23 18:34:22 +01:00
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int numCpus() { return _numCpus; }
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2006-06-28 17:02:14 +02:00
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// Statistics
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/**
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* @addtogroup CacheStatistics
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* @{
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*/
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/** Number of hits per thread for each type of command. @sa Packet::Command */
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2009-03-06 04:09:53 +01:00
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Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** Number of hits for demand accesses. */
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Stats::Formula demandHits;
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/** Number of hit for all accesses. */
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Stats::Formula overallHits;
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/** Number of misses per thread for each type of command. @sa Packet::Command */
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2009-03-06 04:09:53 +01:00
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Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** Number of misses for demand accesses. */
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Stats::Formula demandMisses;
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/** Number of misses for all accesses. */
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Stats::Formula overallMisses;
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/**
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* Total number of cycles per thread/command spent waiting for a miss.
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* Used to calculate the average miss latency.
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*/
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2009-03-06 04:09:53 +01:00
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Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** Total number of cycles spent waiting for demand misses. */
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Stats::Formula demandMissLatency;
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/** Total number of cycles spent waiting for all misses. */
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Stats::Formula overallMissLatency;
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/** The number of accesses per command and thread. */
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2007-02-07 19:53:37 +01:00
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Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** The number of demand accesses. */
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Stats::Formula demandAccesses;
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/** The number of overall accesses. */
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Stats::Formula overallAccesses;
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/** The miss rate per command and thread. */
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2007-02-07 19:53:37 +01:00
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Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** The miss rate of all demand accesses. */
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Stats::Formula demandMissRate;
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/** The miss rate for all accesses. */
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Stats::Formula overallMissRate;
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/** The average miss latency per command and thread. */
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2007-02-07 19:53:37 +01:00
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Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
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2006-06-28 17:02:14 +02:00
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/** The average miss latency for demand misses. */
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Stats::Formula demandAvgMissLatency;
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/** The average miss latency for all misses. */
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Stats::Formula overallAvgMissLatency;
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/** The total number of cycles blocked for each blocked cause. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector blocked_cycles;
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2006-06-28 17:02:14 +02:00
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/** The number of times this cache blocked for each blocked cause. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector blocked_causes;
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2006-06-28 17:02:14 +02:00
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/** The average number of cycles blocked for each blocked cause. */
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Stats::Formula avg_blocked;
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/** The number of fast writes (WH64) performed. */
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2009-03-06 04:09:53 +01:00
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Stats::Scalar fastWrites;
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2006-06-28 17:02:14 +02:00
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/** The number of cache copies performed. */
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2009-03-06 04:09:53 +01:00
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Stats::Scalar cacheCopies;
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2006-06-28 17:02:14 +02:00
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2007-06-18 02:27:53 +02:00
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/** Number of blocks written back per thread. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector writebacks;
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2007-06-18 02:27:53 +02:00
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/** Number of misses that hit in the MSHRs per command and thread. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
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2007-06-18 02:27:53 +02:00
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/** Demand misses that hit in the MSHRs. */
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Stats::Formula demandMshrHits;
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/** Total number of misses that hit in the MSHRs. */
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Stats::Formula overallMshrHits;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
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2007-06-18 02:27:53 +02:00
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/** Demand misses that miss in the MSHRs. */
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Stats::Formula demandMshrMisses;
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrMisses;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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2009-03-06 04:09:53 +01:00
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Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
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2007-06-18 02:27:53 +02:00
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrUncacheable;
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/** Total cycle latency of each MSHR miss, per command and thread. */
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2009-03-06 04:09:53 +01:00
|
|
|
Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
|
2007-06-18 02:27:53 +02:00
|
|
|
/** Total cycle latency of demand MSHR misses. */
|
|
|
|
Stats::Formula demandMshrMissLatency;
|
|
|
|
/** Total cycle latency of overall MSHR misses. */
|
|
|
|
Stats::Formula overallMshrMissLatency;
|
|
|
|
|
|
|
|
/** Total cycle latency of each MSHR miss, per command and thread. */
|
2009-03-06 04:09:53 +01:00
|
|
|
Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
|
2007-06-18 02:27:53 +02:00
|
|
|
/** Total cycle latency of overall MSHR misses. */
|
|
|
|
Stats::Formula overallMshrUncacheableLatency;
|
|
|
|
|
2010-06-15 10:18:36 +02:00
|
|
|
#if 0
|
2007-06-18 02:27:53 +02:00
|
|
|
/** The total number of MSHR accesses per command and thread. */
|
|
|
|
Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
|
|
|
|
/** The total number of demand MSHR accesses. */
|
|
|
|
Stats::Formula demandMshrAccesses;
|
|
|
|
/** The total number of MSHR accesses. */
|
|
|
|
Stats::Formula overallMshrAccesses;
|
2010-06-15 10:18:36 +02:00
|
|
|
#endif
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
/** The miss rate in the MSHRs pre command and thread. */
|
|
|
|
Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
|
|
|
|
/** The demand miss rate in the MSHRs. */
|
|
|
|
Stats::Formula demandMshrMissRate;
|
|
|
|
/** The overall miss rate in the MSHRs. */
|
|
|
|
Stats::Formula overallMshrMissRate;
|
|
|
|
|
|
|
|
/** The average latency of an MSHR miss, per command and thread. */
|
|
|
|
Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
|
|
|
|
/** The average latency of a demand MSHR miss. */
|
|
|
|
Stats::Formula demandAvgMshrMissLatency;
|
|
|
|
/** The average overall latency of an MSHR miss. */
|
|
|
|
Stats::Formula overallAvgMshrMissLatency;
|
|
|
|
|
|
|
|
/** The average latency of an MSHR miss, per command and thread. */
|
|
|
|
Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
|
|
|
|
/** The average overall latency of an MSHR miss. */
|
|
|
|
Stats::Formula overallAvgMshrUncacheableLatency;
|
|
|
|
|
|
|
|
/** The number of times a thread hit its MSHR cap. */
|
2009-03-06 04:09:53 +01:00
|
|
|
Stats::Vector mshr_cap_events;
|
2007-06-18 02:27:53 +02:00
|
|
|
/** The number of times software prefetches caused the MSHR to block. */
|
2009-03-06 04:09:53 +01:00
|
|
|
Stats::Vector soft_prefetch_mshr_full;
|
2007-06-18 02:27:53 +02:00
|
|
|
|
2009-03-06 04:09:53 +01:00
|
|
|
Stats::Scalar mshr_no_allocate_misses;
|
2007-06-18 02:27:53 +02:00
|
|
|
|
2006-06-28 17:02:14 +02:00
|
|
|
/**
|
|
|
|
* @}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Register stats for this object.
|
|
|
|
*/
|
|
|
|
virtual void regStats();
|
|
|
|
|
|
|
|
public:
|
2007-08-30 21:16:59 +02:00
|
|
|
typedef BaseCacheParams Params;
|
|
|
|
BaseCache(const Params *p);
|
|
|
|
~BaseCache() {}
|
2006-11-11 04:45:50 +01:00
|
|
|
|
2006-07-07 22:02:22 +02:00
|
|
|
virtual void init();
|
|
|
|
|
2006-06-28 17:02:14 +02:00
|
|
|
/**
|
|
|
|
* Query block size of a cache.
|
|
|
|
* @return The block size
|
|
|
|
*/
|
2009-06-05 08:21:12 +02:00
|
|
|
unsigned
|
|
|
|
getBlockSize() const
|
2006-06-28 17:02:14 +02:00
|
|
|
{
|
|
|
|
return blkSize;
|
|
|
|
}
|
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
|
2009-09-26 19:50:50 +02:00
|
|
|
Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
|
2008-07-16 20:10:33 +02:00
|
|
|
const Range<Addr> &getAddrRange() const { return addrRange; }
|
|
|
|
|
2007-06-21 20:59:17 +02:00
|
|
|
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
|
|
|
|
{
|
2007-07-21 22:45:17 +02:00
|
|
|
assert(!pkt->req->isUncacheable());
|
2007-06-21 20:59:17 +02:00
|
|
|
return allocateBufferInternal(&mshrQueue,
|
|
|
|
blockAlign(pkt->getAddr()), blkSize,
|
|
|
|
pkt, time, requestBus);
|
|
|
|
}
|
|
|
|
|
2007-07-21 22:45:17 +02:00
|
|
|
MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
|
2007-06-21 20:59:17 +02:00
|
|
|
{
|
2007-07-21 22:45:17 +02:00
|
|
|
assert(pkt->isWrite() && !pkt->isRead());
|
|
|
|
return allocateBufferInternal(&writeBuffer,
|
|
|
|
pkt->getAddr(), pkt->getSize(),
|
2007-06-21 20:59:17 +02:00
|
|
|
pkt, time, requestBus);
|
|
|
|
}
|
|
|
|
|
2007-07-21 22:45:17 +02:00
|
|
|
MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
|
|
|
|
{
|
|
|
|
assert(pkt->req->isUncacheable());
|
|
|
|
assert(pkt->isRead());
|
|
|
|
return allocateBufferInternal(&mshrQueue,
|
|
|
|
pkt->getAddr(), pkt->getSize(),
|
|
|
|
pkt, time, requestBus);
|
|
|
|
}
|
2007-06-21 20:59:17 +02:00
|
|
|
|
2006-06-28 17:02:14 +02:00
|
|
|
/**
|
|
|
|
* Returns true if the cache is blocked for accesses.
|
|
|
|
*/
|
|
|
|
bool isBlocked()
|
|
|
|
{
|
|
|
|
return blocked != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Marks the access path of the cache as blocked for the given cause. This
|
|
|
|
* also sets the blocked flag in the slave interface.
|
|
|
|
* @param cause The reason for the cache blocking.
|
|
|
|
*/
|
|
|
|
void setBlocked(BlockedCause cause)
|
|
|
|
{
|
|
|
|
uint8_t flag = 1 << cause;
|
|
|
|
if (blocked == 0) {
|
|
|
|
blocked_causes[cause]++;
|
|
|
|
blockedCycle = curTick;
|
2007-06-22 18:24:07 +02:00
|
|
|
cpuSidePort->setBlocked();
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
2007-06-22 18:24:07 +02:00
|
|
|
blocked |= flag;
|
|
|
|
DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Marks the cache as unblocked for the given cause. This also clears the
|
|
|
|
* blocked flags in the appropriate interfaces.
|
|
|
|
* @param cause The newly unblocked cause.
|
|
|
|
* @warning Calling this function can cause a blocked request on the bus to
|
|
|
|
* access the cache. The cache must be in a state to handle that request.
|
|
|
|
*/
|
|
|
|
void clearBlocked(BlockedCause cause)
|
|
|
|
{
|
|
|
|
uint8_t flag = 1 << cause;
|
2007-06-22 18:24:07 +02:00
|
|
|
blocked &= ~flag;
|
|
|
|
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
|
|
|
|
if (blocked == 0) {
|
|
|
|
blocked_cycles[cause] += curTick - blockedCycle;
|
|
|
|
cpuSidePort->clearBlocked();
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Request the master bus for the given cause and time.
|
|
|
|
* @param cause The reason for the request.
|
|
|
|
* @param time The time to make the request.
|
|
|
|
*/
|
2007-05-19 07:35:04 +02:00
|
|
|
void requestMemSideBus(RequestCause cause, Tick time)
|
2006-06-28 17:02:14 +02:00
|
|
|
{
|
2007-05-19 07:35:04 +02:00
|
|
|
memSidePort->requestBus(cause, time);
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Clear the master bus request for the given cause.
|
|
|
|
* @param cause The request reason to clear.
|
|
|
|
*/
|
2007-05-19 07:35:04 +02:00
|
|
|
void deassertMemSideBusRequest(RequestCause cause)
|
2006-06-28 17:02:14 +02:00
|
|
|
{
|
2009-02-16 17:56:40 +01:00
|
|
|
// Obsolete... we no longer signal bus requests explicitly so
|
|
|
|
// we can't deassert them. Leaving this in as a no-op since
|
|
|
|
// the prefetcher calls it to indicate that it no longer wants
|
|
|
|
// to request a prefetch, and someday that might be
|
|
|
|
// interesting again.
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
virtual unsigned int drain(Event *de);
|
2006-06-28 17:02:14 +02:00
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
virtual bool inCache(Addr addr) = 0;
|
2006-11-07 20:25:54 +01:00
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
virtual bool inMissQueue(Addr addr) = 0;
|
2006-11-07 20:25:54 +01:00
|
|
|
|
2010-02-23 18:34:22 +01:00
|
|
|
void incMissCount(PacketPtr pkt, int id)
|
2006-11-07 20:25:54 +01:00
|
|
|
{
|
2010-02-23 18:34:22 +01:00
|
|
|
|
|
|
|
if (pkt->cmd == MemCmd::Writeback) {
|
|
|
|
assert(id == -1);
|
|
|
|
misses[pkt->cmdToIndex()][0]++;
|
|
|
|
/* same thing for writeback hits as misses - no context id
|
|
|
|
* available, meanwhile writeback hit/miss stats are not used
|
|
|
|
* in any aggregate hit/miss calculations, so just lump them all
|
|
|
|
* in bucket 0 */
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
} else if (id == -1) {
|
|
|
|
// Device accesses have id -1
|
|
|
|
// lump device accesses into their own bucket
|
|
|
|
misses[pkt->cmdToIndex()][_numCpus]++;
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
misses[pkt->cmdToIndex()][id % _numCpus]++;
|
|
|
|
}
|
2006-11-07 20:25:54 +01:00
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
if (missCount) {
|
|
|
|
--missCount;
|
|
|
|
if (missCount == 0)
|
|
|
|
exitSimLoop("A cache reached the maximum miss count");
|
2006-11-07 20:25:54 +01:00
|
|
|
}
|
|
|
|
}
|
2010-02-23 18:34:22 +01:00
|
|
|
void incHitCount(PacketPtr pkt, int id)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* Writeback requests don't have a context id associated with
|
|
|
|
* them, so attributing a hit to a -1 context id is obviously a
|
|
|
|
* problem. I've noticed in the stats that hits are split into
|
|
|
|
* demand and non-demand hits - neither of which include writeback
|
|
|
|
* hits, so here, I'll just put the writeback hits into bucket 0
|
|
|
|
* since it won't mess with any other stats -hsul */
|
|
|
|
if (pkt->cmd == MemCmd::Writeback) {
|
|
|
|
assert(id == -1);
|
|
|
|
hits[pkt->cmdToIndex()][0]++;
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
} else if (id == -1) {
|
|
|
|
// Device accesses have id -1
|
|
|
|
// lump device accesses into their own bucket
|
|
|
|
hits[pkt->cmdToIndex()][_numCpus]++;
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* the % is necessary in case there are switch cpus */
|
|
|
|
hits[pkt->cmdToIndex()][id % _numCpus]++;
|
|
|
|
}
|
|
|
|
}
|
2006-12-19 06:53:06 +01:00
|
|
|
|
2006-06-28 17:02:14 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif //__BASE_CACHE_HH__
|