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gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout

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add a sparc fs regression src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress --HG-- extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-04 04:45:26 +01:00
M5 Simulator System
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
Copyright (c) 2001-2008
add a sparc fs regression src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress --HG-- extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-04 04:45:26 +01:00
The Regents of The University of Michigan
All Rights Reserved
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
M5 compiled Nov 5 2008 15:59:58
M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e
M5 commit date Wed Nov 05 15:30:49 2008 -0500
M5 started Nov 5 2008 16:00:22
M5 executing on zizzer
tests: Update all tests for small outstanding changes. Little differences have accumulated over time and it's worth getting things back in sync for the stable release.
2008-09-28 23:16:26 +02:00
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
fixed sttw instruction changes execution trace a bit --HG-- extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
2007-04-04 00:28:59 +02:00
Global frequency set at 2000000000 ticks per second
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
fixed sttw instruction changes execution trace a bit --HG-- extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
2007-04-04 00:28:59 +02:00
Exiting @ tick 2233777512 because m5_exit instruction encountered
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