gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Apr 22 2015 08:08:31
gem5 started Apr 22 2015 08:14:03
gem5 executing on phenom
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing

Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB:		Passed
SWAP:		Passed
CAS FAIL:	Passed
CAS WORK:	Passed
CASX FAIL:	Passed
CASX WORK:	Passed
LDTX:		Passed
LDTW:		Passed
STTW:		Passed
Done
Exiting @ tick 27482500 because target called exit()
sparc: update o3 regressions 2011-06-11 04:15:34 +02:00			`gem5 Simulator System. http://gem5.org`
			`gem5 is copyrighted software; use the --copyright option for details.`
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. 2008-07-22 23:00:18 +02:00
stats: update for previous changeset Very small differences in IQ-specific O3 stats. 2015-04-23 05:22:29 +02:00			`gem5 compiled Apr 22 2015 08:08:31`
			`gem5 started Apr 22 2015 08:14:03`
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. 2014-06-22 23:33:09 +02:00			`gem5 executing on phenom`
			`command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing`
stats: update for previous changeset Very small differences in IQ-specific O3 stats. 2015-04-23 05:22:29 +02:00
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. 2008-07-22 23:00:18 +02:00			`Global frequency set at 1000000000000 ticks per second`
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. 2008-11-06 17:11:42 +01:00			`info: Entering event queue @ 0. Starting simulation...`
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19 2007-04-09 09:59:56 +02:00			`Begining test of difficult SPARC instructions...`
			`LDSTUB: Passed`
			`SWAP: Passed`
			`CAS FAIL: Passed`
			`CAS WORK: Passed`
			`CASX FAIL: Passed`
			`CASX WORK: Passed`
			`LDTX: Passed`
			`LDTW: Passed`
			`STTW: Passed`
			`Done`
stats: update for previous changeset Very small differences in IQ-specific O3 stats. 2015-04-23 05:22:29 +02:00			`Exiting @ tick 27482500 because target called exit()`