2004-03-23 23:10:07 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-03-23 23:10:07 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Andrew Schultz
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* Ali Saidi
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* Miguel Serrano
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2004-03-23 23:10:07 +01:00
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*/
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#include <cstddef>
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#include <cstdlib>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "dev/ide_ctrl.hh"
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2004-11-13 20:01:38 +01:00
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#include "dev/ide_disk.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pcireg.h"
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#include "dev/platform.hh"
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2006-04-20 23:14:30 +02:00
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#include "mem/packet.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet_access.hh"
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2004-03-23 23:10:07 +01:00
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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2006-04-20 23:14:30 +02:00
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#include "sim/byteswap.hh"
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2004-03-23 23:10:07 +01:00
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using namespace std;
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////
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// Initialization and destruction
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////
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2004-11-13 21:45:22 +01:00
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IdeController::IdeController(Params *p)
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: PciDev(p)
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2004-03-23 23:10:07 +01:00
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{
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// initialize the PIO interface addresses
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pri_cmd_addr = 0;
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pri_cmd_size = BARSize[0];
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pri_ctrl_addr = 0;
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pri_ctrl_size = BARSize[1];
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sec_cmd_addr = 0;
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sec_cmd_size = BARSize[2];
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sec_ctrl_addr = 0;
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sec_ctrl_size = BARSize[3];
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// initialize the bus master interface (BMI) address to be configured
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// via PCI
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bmi_addr = 0;
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bmi_size = BARSize[4];
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// zero out all of the registers
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2005-08-15 22:59:58 +02:00
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memset(bmi_regs.data, 0, sizeof(bmi_regs));
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memset(config_regs.data, 0, sizeof(config_regs.data));
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2004-03-23 23:10:07 +01:00
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// setup initial values
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2005-08-15 22:59:58 +02:00
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// enable both channels
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config_regs.idetim0 = htole((uint16_t)IDETIM_DECODE_EN);
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config_regs.idetim1 = htole((uint16_t)IDETIM_DECODE_EN);
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bmi_regs.bmis0 = DMA1CAP | DMA0CAP;
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bmi_regs.bmis1 = DMA1CAP | DMA0CAP;
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2004-03-23 23:10:07 +01:00
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// reset all internal variables
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io_enabled = false;
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bm_enabled = false;
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memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
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// setup the disks attached to controller
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2005-08-23 17:45:52 +02:00
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memset(disks, 0, sizeof(disks));
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2005-06-30 04:16:40 +02:00
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dev[0] = 0;
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dev[1] = 0;
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2004-03-23 23:10:07 +01:00
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2004-11-13 21:45:22 +01:00
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if (params()->disks.size() > 3)
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2004-03-23 23:10:07 +01:00
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panic("IDE controllers support a maximum of 4 devices attached!\n");
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2004-11-13 21:45:22 +01:00
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for (int i = 0; i < params()->disks.size(); i++) {
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disks[i] = params()->disks[i];
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2006-04-20 23:14:30 +02:00
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disks[i]->setController(this);
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2004-03-23 23:10:07 +01:00
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}
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}
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IdeController::~IdeController()
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{
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for (int i = 0; i < 4; i++)
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if (disks[i])
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delete disks[i];
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}
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2004-05-12 22:55:49 +02:00
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////
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// Utility functions
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///
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void
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2005-08-15 22:59:58 +02:00
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IdeController::parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
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IdeRegType ®_type)
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2004-05-12 22:55:49 +02:00
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{
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offset = addr;
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if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
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offset -= pri_cmd_addr;
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2005-08-15 22:59:58 +02:00
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reg_type = COMMAND_BLOCK;
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channel = PRIMARY;
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2004-05-12 22:55:49 +02:00
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} else if (addr >= pri_ctrl_addr &&
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addr < (pri_ctrl_addr + pri_ctrl_size)) {
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offset -= pri_ctrl_addr;
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2005-08-15 22:59:58 +02:00
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reg_type = CONTROL_BLOCK;
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channel = PRIMARY;
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2004-05-12 22:55:49 +02:00
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} else if (addr >= sec_cmd_addr &&
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addr < (sec_cmd_addr + sec_cmd_size)) {
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offset -= sec_cmd_addr;
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2005-08-15 22:59:58 +02:00
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reg_type = COMMAND_BLOCK;
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channel = SECONDARY;
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2004-05-12 22:55:49 +02:00
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} else if (addr >= sec_ctrl_addr &&
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addr < (sec_ctrl_addr + sec_ctrl_size)) {
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offset -= sec_ctrl_addr;
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2005-08-15 22:59:58 +02:00
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reg_type = CONTROL_BLOCK;
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channel = SECONDARY;
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2004-05-12 22:55:49 +02:00
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} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
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offset -= bmi_addr;
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2005-08-15 22:59:58 +02:00
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reg_type = BMI_BLOCK;
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channel = (offset < BMIC1) ? PRIMARY : SECONDARY;
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2004-05-12 22:55:49 +02:00
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} else {
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panic("IDE controller access to invalid address: %#x\n", addr);
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}
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}
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int
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2005-08-15 22:59:58 +02:00
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IdeController::getDisk(IdeChannel channel)
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2004-05-12 22:55:49 +02:00
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{
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int disk = 0;
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uint8_t *devBit = &dev[0];
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2005-08-15 22:59:58 +02:00
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if (channel == SECONDARY) {
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2004-05-12 22:55:49 +02:00
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disk += 2;
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devBit = &dev[1];
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}
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disk += *devBit;
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assert(*devBit == 0 || *devBit == 1);
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return disk;
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}
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int
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IdeController::getDisk(IdeDisk *diskPtr)
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{
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for (int i = 0; i < 4; i++) {
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if ((long)diskPtr == (long)disks[i])
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return i;
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}
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return -1;
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}
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2004-06-23 21:37:05 +02:00
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bool
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IdeController::isDiskSelected(IdeDisk *diskPtr)
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{
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for (int i = 0; i < 4; i++) {
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if ((long)diskPtr == (long)disks[i]) {
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// is disk is on primary or secondary channel
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int channel = i/2;
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// is disk the master or slave
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int devID = i%2;
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return (dev[channel] == devID);
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}
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}
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panic("Unable to find disk by pointer!!\n");
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}
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2004-05-03 17:47:52 +02:00
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////
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// Command completion
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////
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void
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IdeController::setDmaComplete(IdeDisk *disk)
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{
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int diskNum = getDisk(disk);
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if (diskNum < 0)
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panic("Unable to find disk based on pointer %#x\n", disk);
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if (diskNum < 2) {
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// clear the start/stop bit in the command register
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmic0 &= ~SSBM;
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2004-05-03 17:47:52 +02:00
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// clear the bus master active bit in the status register
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmis0 &= ~BMIDEA;
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2004-05-03 17:47:52 +02:00
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// set the interrupt bit
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmis0 |= IDEINTS;
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2004-05-03 17:47:52 +02:00
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} else {
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// clear the start/stop bit in the command register
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmic1 &= ~SSBM;
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2004-05-03 17:47:52 +02:00
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// clear the bus master active bit in the status register
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmis1 &= ~BMIDEA;
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2004-05-03 17:47:52 +02:00
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// set the interrupt bit
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2005-08-15 22:59:58 +02:00
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bmi_regs.bmis1 |= IDEINTS;
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2004-05-03 17:47:52 +02:00
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}
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}
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2004-03-23 23:10:07 +01:00
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////
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// Read and write handling
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////
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2006-07-06 20:41:01 +02:00
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Tick
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2006-10-20 09:10:12 +02:00
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IdeController::readConfig(PacketPtr pkt)
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2004-03-23 23:10:07 +01:00
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{
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2006-07-06 20:41:01 +02:00
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset < PCI_DEVICE_SPECIFIC)
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return PciDev::readConfig(pkt);
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assert(offset >= IDE_CTRL_CONF_START && (offset + 1) <= IDE_CTRL_CONF_END);
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2005-08-15 22:59:58 +02:00
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2006-07-06 20:41:01 +02:00
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pkt->allocate();
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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2006-04-20 23:14:30 +02:00
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switch (offset) {
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case IDE_CTRL_CONF_DEV_TIMING:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(config_regs.sidetim);
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2005-08-15 22:59:58 +02:00
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break;
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2006-04-20 23:14:30 +02:00
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case IDE_CTRL_CONF_UDMA_CNTRL:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(config_regs.udmactl);
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2005-08-15 22:59:58 +02:00
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break;
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2006-04-20 23:14:30 +02:00
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case IDE_CTRL_CONF_PRIM_TIMING+1:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(htole(config_regs.idetim0) >> 8);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_SEC_TIMING+1:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(htole(config_regs.idetim1) >> 8);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_IDE_CONFIG:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(htole(config_regs.ideconfig) & 0xFF);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_IDE_CONFIG+1:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint8_t>(htole(config_regs.ideconfig) >> 8);
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2005-08-15 22:59:58 +02:00
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break;
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default:
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2006-04-20 23:14:30 +02:00
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panic("Invalid PCI configuration read for size 1 at offset: %#x!\n",
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offset);
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2004-03-23 23:10:07 +01:00
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}
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2006-07-06 20:41:01 +02:00
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 1 data: %#x\n", offset,
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(uint32_t)pkt->get<uint8_t>());
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break;
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case sizeof(uint16_t):
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2006-04-20 23:14:30 +02:00
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switch (offset) {
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case IDE_CTRL_CONF_PRIM_TIMING:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint16_t>(config_regs.idetim0);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_SEC_TIMING:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint16_t>(config_regs.idetim1);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_UDMA_TIMING:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint16_t>(config_regs.udmatim);
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2006-04-20 23:14:30 +02:00
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break;
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case IDE_CTRL_CONF_IDE_CONFIG:
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2006-07-06 20:41:01 +02:00
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pkt->set<uint16_t>(config_regs.ideconfig);
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2006-04-20 23:14:30 +02:00
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break;
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default:
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panic("Invalid PCI configuration read for size 2 offset: %#x!\n",
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offset);
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}
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2006-07-06 20:41:01 +02:00
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 2 data: %#x\n", offset,
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(uint32_t)pkt->get<uint16_t>());
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break;
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case sizeof(uint32_t):
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panic("No 32bit reads implemented for this device.");
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DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset,
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(uint32_t)pkt->get<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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2006-04-20 23:14:30 +02:00
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}
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2006-07-06 20:41:01 +02:00
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pkt->result = Packet::Success;
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return configDelay;
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2006-04-20 23:14:30 +02:00
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}
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2005-08-15 22:59:58 +02:00
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2006-07-06 20:41:01 +02:00
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Tick
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2006-10-20 09:10:12 +02:00
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IdeController::writeConfig(PacketPtr pkt)
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2006-04-20 23:14:30 +02:00
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{
|
2006-07-06 20:41:01 +02:00
|
|
|
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
|
2006-04-20 23:14:30 +02:00
|
|
|
if (offset < PCI_DEVICE_SPECIFIC) {
|
2006-07-06 20:41:01 +02:00
|
|
|
PciDev::writeConfig(pkt);
|
|
|
|
} else {
|
|
|
|
assert(offset >= IDE_CTRL_CONF_START && (offset + 1) <= IDE_CTRL_CONF_END);
|
2006-04-20 23:14:30 +02:00
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
switch (pkt->getSize()) {
|
|
|
|
case sizeof(uint8_t):
|
|
|
|
switch (offset) {
|
|
|
|
case IDE_CTRL_CONF_DEV_TIMING:
|
|
|
|
config_regs.sidetim = pkt->get<uint8_t>();
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_UDMA_CNTRL:
|
|
|
|
config_regs.udmactl = pkt->get<uint8_t>();
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_IDE_CONFIG:
|
|
|
|
config_regs.ideconfig = (config_regs.ideconfig & 0xFF00) |
|
|
|
|
(pkt->get<uint8_t>());
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_IDE_CONFIG+1:
|
|
|
|
config_regs.ideconfig = (config_regs.ideconfig & 0x00FF) |
|
|
|
|
pkt->get<uint8_t>() << 8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Invalid PCI configuration write for size 1 offset: %#x!\n",
|
|
|
|
offset);
|
|
|
|
}
|
|
|
|
DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
|
|
|
|
offset, (uint32_t)pkt->get<uint8_t>());
|
2005-09-13 04:53:57 +02:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case sizeof(uint16_t):
|
|
|
|
switch (offset) {
|
|
|
|
case IDE_CTRL_CONF_PRIM_TIMING:
|
|
|
|
config_regs.idetim0 = pkt->get<uint16_t>();
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_SEC_TIMING:
|
|
|
|
config_regs.idetim1 = pkt->get<uint16_t>();
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_UDMA_TIMING:
|
|
|
|
config_regs.udmatim = pkt->get<uint16_t>();
|
|
|
|
break;
|
|
|
|
case IDE_CTRL_CONF_IDE_CONFIG:
|
|
|
|
config_regs.ideconfig = pkt->get<uint16_t>();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Invalid PCI configuration write for size 2 offset: %#x!\n",
|
|
|
|
offset);
|
|
|
|
}
|
|
|
|
DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n",
|
|
|
|
offset, (uint32_t)pkt->get<uint16_t>());
|
2006-04-20 23:14:30 +02:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
case sizeof(uint32_t):
|
|
|
|
panic("Write of unimplemented PCI config. register: %x\n", offset);
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
default:
|
2006-07-06 20:41:01 +02:00
|
|
|
panic("invalid access size(?) for PCI configspace!\n");
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
/* Trap command register writes and enable IO/BM as appropriate as well as
|
|
|
|
* BARs. */
|
2006-04-20 23:14:30 +02:00
|
|
|
switch(offset) {
|
2004-06-04 21:12:27 +02:00
|
|
|
case PCI0_BASE_ADDR0:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (BARAddrs[0] != 0)
|
2004-03-23 23:10:07 +01:00
|
|
|
pri_cmd_addr = BARAddrs[0];
|
2004-06-04 21:12:27 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-06-04 21:12:27 +02:00
|
|
|
case PCI0_BASE_ADDR1:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (BARAddrs[1] != 0)
|
2004-03-23 23:10:07 +01:00
|
|
|
pri_ctrl_addr = BARAddrs[1];
|
2004-06-04 21:12:27 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-06-04 21:12:27 +02:00
|
|
|
case PCI0_BASE_ADDR2:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (BARAddrs[2] != 0)
|
2004-03-23 23:10:07 +01:00
|
|
|
sec_cmd_addr = BARAddrs[2];
|
2004-06-04 21:12:27 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-06-04 21:12:27 +02:00
|
|
|
case PCI0_BASE_ADDR3:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (BARAddrs[3] != 0)
|
2004-03-23 23:10:07 +01:00
|
|
|
sec_ctrl_addr = BARAddrs[3];
|
2004-06-04 21:12:27 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-06-04 21:12:27 +02:00
|
|
|
case PCI0_BASE_ADDR4:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (BARAddrs[4] != 0)
|
2004-03-23 23:10:07 +01:00
|
|
|
bmi_addr = BARAddrs[4];
|
2004-06-04 21:12:27 +02:00
|
|
|
break;
|
2006-07-06 20:41:01 +02:00
|
|
|
|
|
|
|
case PCI_COMMAND:
|
|
|
|
if (letoh(config.command) & PCI_CMD_IOSE)
|
|
|
|
io_enabled = true;
|
|
|
|
else
|
|
|
|
io_enabled = false;
|
|
|
|
|
|
|
|
if (letoh(config.command) & PCI_CMD_BME)
|
|
|
|
bm_enabled = true;
|
|
|
|
else
|
|
|
|
bm_enabled = false;
|
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
2006-07-06 20:41:01 +02:00
|
|
|
pkt->result = Packet::Success;
|
|
|
|
return configDelay;
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
|
2006-04-20 23:14:30 +02:00
|
|
|
Tick
|
2006-10-20 09:10:12 +02:00
|
|
|
IdeController::read(PacketPtr pkt)
|
2004-03-23 23:10:07 +01:00
|
|
|
{
|
2004-05-03 17:47:52 +02:00
|
|
|
Addr offset;
|
2005-08-15 22:59:58 +02:00
|
|
|
IdeChannel channel;
|
|
|
|
IdeRegType reg_type;
|
2004-05-03 17:47:52 +02:00
|
|
|
int disk;
|
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->allocate();
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != 1 && pkt->getSize() != 2 && pkt->getSize() !=4)
|
|
|
|
panic("Bad IDE read size: %d\n", pkt->getSize());
|
2006-04-20 23:14:30 +02:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
parseAddr(pkt->getAddr(), offset, channel, reg_type);
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2006-04-20 23:14:30 +02:00
|
|
|
if (!io_enabled) {
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->result = Packet::Success;
|
2006-04-20 23:14:30 +02:00
|
|
|
return pioDelay;
|
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
switch (reg_type) {
|
|
|
|
case BMI_BLOCK:
|
2006-05-26 20:17:33 +02:00
|
|
|
switch (pkt->getSize()) {
|
2005-08-15 22:59:58 +02:00
|
|
|
case sizeof(uint8_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set(bmi_regs.data[offset]);
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
case sizeof(uint16_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set(*(uint16_t*)&bmi_regs.data[offset]);
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
case sizeof(uint32_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set(*(uint32_t*)&bmi_regs.data[offset]);
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
panic("IDE read of BMI reg invalid size: %#x\n", pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case COMMAND_BLOCK:
|
|
|
|
case CONTROL_BLOCK:
|
|
|
|
disk = getDisk(channel);
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
if (disks[disk] == NULL) {
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->set<uint8_t>(0);
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
2006-04-25 01:31:50 +02:00
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
switch (offset) {
|
|
|
|
case DATA_OFFSET:
|
2006-05-26 20:17:33 +02:00
|
|
|
switch (pkt->getSize()) {
|
2005-08-15 22:59:58 +02:00
|
|
|
case sizeof(uint16_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>());
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case sizeof(uint32_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>());
|
2006-04-25 01:31:50 +02:00
|
|
|
disks[disk]->read(offset, reg_type,
|
2006-05-19 04:32:21 +02:00
|
|
|
pkt->getPtr<uint8_t>() + sizeof(uint16_t));
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
panic("IDE read of data reg invalid size: %#x\n", pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == sizeof(uint8_t)) {
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->read(offset, reg_type, pkt->getPtr<uint8_t>());
|
2005-08-15 22:59:58 +02:00
|
|
|
} else
|
2006-05-26 20:17:33 +02:00
|
|
|
panic("IDE read of command reg of invalid size: %#x\n", pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("IDE controller read of unknown register block type!\n");
|
2004-05-03 17:47:52 +02:00
|
|
|
}
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == 1)
|
2005-04-06 23:39:25 +02:00
|
|
|
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), (uint32_t)pkt->get<uint8_t>());
|
|
|
|
else if (pkt->getSize() == 2)
|
2006-04-20 23:14:30 +02:00
|
|
|
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), pkt->get<uint16_t>());
|
2006-04-20 23:14:30 +02:00
|
|
|
else
|
|
|
|
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), pkt->get<uint32_t>());
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->result = Packet::Success;
|
2006-04-20 23:14:30 +02:00
|
|
|
return pioDelay;
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
2006-04-20 23:14:30 +02:00
|
|
|
Tick
|
2006-10-20 09:10:12 +02:00
|
|
|
IdeController::write(PacketPtr pkt)
|
2004-03-23 23:10:07 +01:00
|
|
|
{
|
2004-05-03 17:47:52 +02:00
|
|
|
Addr offset;
|
2005-08-15 22:59:58 +02:00
|
|
|
IdeChannel channel;
|
|
|
|
IdeRegType reg_type;
|
2004-05-03 17:47:52 +02:00
|
|
|
int disk;
|
|
|
|
uint8_t oldVal, newVal;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
parseAddr(pkt->getAddr(), offset, channel, reg_type);
|
2006-04-20 23:14:30 +02:00
|
|
|
|
|
|
|
if (!io_enabled) {
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->result = Packet::Success;
|
2006-04-25 01:31:50 +02:00
|
|
|
DPRINTF(IdeCtrl, "io not enabled\n");
|
2006-04-20 23:14:30 +02:00
|
|
|
return pioDelay;
|
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
switch (reg_type) {
|
|
|
|
case BMI_BLOCK:
|
2006-04-20 23:14:30 +02:00
|
|
|
if (!bm_enabled) {
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->result = Packet::Success;
|
2006-04-20 23:14:30 +02:00
|
|
|
return pioDelay;
|
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
switch (offset) {
|
|
|
|
// Bus master IDE command register
|
|
|
|
case BMIC1:
|
|
|
|
case BMIC0:
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != sizeof(uint8_t))
|
|
|
|
panic("Invalid BMIC write size: %x\n", pkt->getSize());
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// select the current disk based on DEV bit
|
2005-08-15 22:59:58 +02:00
|
|
|
disk = getDisk(channel);
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-19 23:10:17 +02:00
|
|
|
oldVal = bmi_regs.chan[channel].bmic;
|
2006-05-19 04:32:21 +02:00
|
|
|
newVal = pkt->get<uint8_t>();
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// if a DMA transfer is in progress, R/W control cannot change
|
|
|
|
if (oldVal & SSBM) {
|
|
|
|
if ((oldVal & RWCON) ^ (newVal & RWCON)) {
|
|
|
|
(oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
|
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// see if the start/stop bit is being changed
|
|
|
|
if ((oldVal & SSBM) ^ (newVal & SSBM)) {
|
|
|
|
if (oldVal & SSBM) {
|
|
|
|
// stopping DMA transfer
|
|
|
|
DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
|
|
|
|
|
|
|
|
// clear the BMIDEA bit
|
2005-08-19 23:10:17 +02:00
|
|
|
bmi_regs.chan[channel].bmis =
|
|
|
|
bmi_regs.chan[channel].bmis & ~BMIDEA;
|
2004-05-03 17:47:52 +02:00
|
|
|
|
|
|
|
if (disks[disk] == NULL)
|
|
|
|
panic("DMA stop for disk %d which does not exist\n",
|
|
|
|
disk);
|
|
|
|
|
|
|
|
// inform the disk of the DMA transfer abort
|
|
|
|
disks[disk]->abortDma();
|
|
|
|
} else {
|
|
|
|
// starting DMA transfer
|
|
|
|
DPRINTF(IdeCtrl, "Starting DMA transfer\n");
|
|
|
|
|
|
|
|
// set the BMIDEA bit
|
2005-08-19 23:10:17 +02:00
|
|
|
bmi_regs.chan[channel].bmis =
|
|
|
|
bmi_regs.chan[channel].bmis | BMIDEA;
|
2004-05-03 17:47:52 +02:00
|
|
|
|
|
|
|
if (disks[disk] == NULL)
|
|
|
|
panic("DMA start for disk %d which does not exist\n",
|
|
|
|
disk);
|
|
|
|
|
|
|
|
// inform the disk of the DMA transfer start
|
2005-08-15 22:59:58 +02:00
|
|
|
disks[disk]->startDma(letoh(bmi_regs.chan[channel].bmidtp));
|
2004-05-03 17:47:52 +02:00
|
|
|
}
|
|
|
|
}
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// update the register value
|
2005-08-19 23:10:17 +02:00
|
|
|
bmi_regs.chan[channel].bmic = newVal;
|
2004-05-03 17:47:52 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// Bus master IDE status register
|
|
|
|
case BMIS0:
|
|
|
|
case BMIS1:
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != sizeof(uint8_t))
|
|
|
|
panic("Invalid BMIS write size: %x\n", pkt->getSize());
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-19 23:10:17 +02:00
|
|
|
oldVal = bmi_regs.chan[channel].bmis;
|
2006-05-19 04:32:21 +02:00
|
|
|
newVal = pkt->get<uint8_t>();
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// the BMIDEA bit is RO
|
|
|
|
newVal |= (oldVal & BMIDEA);
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
|
|
|
|
if ((oldVal & IDEINTS) && (newVal & IDEINTS))
|
|
|
|
newVal &= ~IDEINTS; // clear the interrupt?
|
|
|
|
else
|
|
|
|
(oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
|
|
|
|
newVal &= ~IDEDMAE;
|
|
|
|
else
|
|
|
|
(oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2005-08-19 23:10:17 +02:00
|
|
|
bmi_regs.chan[channel].bmis = newVal;
|
2004-05-03 17:47:52 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// Bus master IDE descriptor table pointer register
|
|
|
|
case BMIDTP0:
|
|
|
|
case BMIDTP1:
|
2005-08-19 23:10:17 +02:00
|
|
|
{
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != sizeof(uint32_t))
|
|
|
|
panic("Invalid BMIDTP write size: %x\n", pkt->getSize());
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2006-05-19 04:32:21 +02:00
|
|
|
bmi_regs.chan[channel].bmidtp = htole(pkt->get<uint32_t>() & ~0x3);
|
2005-08-19 23:10:17 +02:00
|
|
|
}
|
2004-05-03 17:47:52 +02:00
|
|
|
break;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() != sizeof(uint8_t) &&
|
|
|
|
pkt->getSize() != sizeof(uint16_t) &&
|
|
|
|
pkt->getSize() != sizeof(uint32_t))
|
2004-05-03 17:47:52 +02:00
|
|
|
panic("IDE controller write of invalid write size: %x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->getSize());
|
2004-03-23 23:10:07 +01:00
|
|
|
|
2004-05-03 17:47:52 +02:00
|
|
|
// do a default copy of data into the registers
|
2006-05-26 20:17:33 +02:00
|
|
|
memcpy(&bmi_regs.data[offset], pkt->getPtr<uint8_t>(), pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case COMMAND_BLOCK:
|
|
|
|
if (offset == IDE_SELECT_OFFSET) {
|
|
|
|
uint8_t *devBit = &dev[channel];
|
2006-05-19 04:32:21 +02:00
|
|
|
*devBit = (letoh(pkt->get<uint8_t>()) & IDE_SELECT_DEV_BIT) ? 1 : 0;
|
2004-05-03 17:47:52 +02:00
|
|
|
}
|
2005-08-15 22:59:58 +02:00
|
|
|
// fall-through ok!
|
|
|
|
case CONTROL_BLOCK:
|
|
|
|
disk = getDisk(channel);
|
|
|
|
|
|
|
|
if (disks[disk] == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case DATA_OFFSET:
|
2006-05-26 20:17:33 +02:00
|
|
|
switch (pkt->getSize()) {
|
2005-08-15 22:59:58 +02:00
|
|
|
case sizeof(uint16_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>());
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case sizeof(uint32_t):
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>());
|
|
|
|
disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>() +
|
2006-04-20 23:14:30 +02:00
|
|
|
sizeof(uint16_t));
|
2005-08-15 22:59:58 +02:00
|
|
|
break;
|
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
panic("IDE write of data reg invalid size: %#x\n", pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == sizeof(uint8_t)) {
|
2006-05-19 04:32:21 +02:00
|
|
|
disks[disk]->write(offset, reg_type, pkt->getPtr<uint8_t>());
|
2005-08-15 22:59:58 +02:00
|
|
|
} else
|
2006-05-26 20:17:33 +02:00
|
|
|
panic("IDE write of command reg of invalid size: %#x\n", pkt->getSize());
|
2005-08-15 22:59:58 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("IDE controller write of unknown register block type!\n");
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
if (pkt->getSize() == 1)
|
2006-04-20 23:14:30 +02:00
|
|
|
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), (uint32_t)pkt->get<uint8_t>());
|
|
|
|
else if (pkt->getSize() == 2)
|
2005-08-15 22:59:58 +02:00
|
|
|
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), pkt->get<uint16_t>());
|
2006-04-20 23:14:30 +02:00
|
|
|
else
|
|
|
|
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
|
2006-05-26 20:17:33 +02:00
|
|
|
offset, pkt->getSize(), pkt->get<uint32_t>());
|
2006-04-20 23:14:30 +02:00
|
|
|
|
2005-08-15 22:59:58 +02:00
|
|
|
|
2006-05-26 20:17:33 +02:00
|
|
|
pkt->result = Packet::Success;
|
2006-04-20 23:14:30 +02:00
|
|
|
return pioDelay;
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
////
|
|
|
|
// Serialization
|
|
|
|
////
|
|
|
|
|
|
|
|
void
|
|
|
|
IdeController::serialize(std::ostream &os)
|
|
|
|
{
|
2004-06-04 21:12:27 +02:00
|
|
|
// Serialize the PciDev base class
|
|
|
|
PciDev::serialize(os);
|
|
|
|
|
2004-05-12 22:55:49 +02:00
|
|
|
// Serialize register addresses and sizes
|
|
|
|
SERIALIZE_SCALAR(pri_cmd_addr);
|
|
|
|
SERIALIZE_SCALAR(pri_cmd_size);
|
|
|
|
SERIALIZE_SCALAR(pri_ctrl_addr);
|
|
|
|
SERIALIZE_SCALAR(pri_ctrl_size);
|
|
|
|
SERIALIZE_SCALAR(sec_cmd_addr);
|
|
|
|
SERIALIZE_SCALAR(sec_cmd_size);
|
|
|
|
SERIALIZE_SCALAR(sec_ctrl_addr);
|
|
|
|
SERIALIZE_SCALAR(sec_ctrl_size);
|
|
|
|
SERIALIZE_SCALAR(bmi_addr);
|
|
|
|
SERIALIZE_SCALAR(bmi_size);
|
|
|
|
|
|
|
|
// Serialize registers
|
2005-08-23 17:45:52 +02:00
|
|
|
SERIALIZE_ARRAY(bmi_regs.data,
|
|
|
|
sizeof(bmi_regs.data) / sizeof(bmi_regs.data[0]));
|
|
|
|
SERIALIZE_ARRAY(dev, sizeof(dev) / sizeof(dev[0]));
|
|
|
|
SERIALIZE_ARRAY(config_regs.data,
|
|
|
|
sizeof(config_regs.data) / sizeof(config_regs.data[0]));
|
2004-05-12 22:55:49 +02:00
|
|
|
|
|
|
|
// Serialize internal state
|
|
|
|
SERIALIZE_SCALAR(io_enabled);
|
|
|
|
SERIALIZE_SCALAR(bm_enabled);
|
2005-08-23 17:45:52 +02:00
|
|
|
SERIALIZE_ARRAY(cmd_in_progress,
|
|
|
|
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
IdeController::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
{
|
2004-06-04 21:12:27 +02:00
|
|
|
// Unserialize the PciDev base class
|
|
|
|
PciDev::unserialize(cp, section);
|
|
|
|
|
2004-05-12 22:55:49 +02:00
|
|
|
// Unserialize register addresses and sizes
|
|
|
|
UNSERIALIZE_SCALAR(pri_cmd_addr);
|
|
|
|
UNSERIALIZE_SCALAR(pri_cmd_size);
|
|
|
|
UNSERIALIZE_SCALAR(pri_ctrl_addr);
|
|
|
|
UNSERIALIZE_SCALAR(pri_ctrl_size);
|
|
|
|
UNSERIALIZE_SCALAR(sec_cmd_addr);
|
|
|
|
UNSERIALIZE_SCALAR(sec_cmd_size);
|
|
|
|
UNSERIALIZE_SCALAR(sec_ctrl_addr);
|
|
|
|
UNSERIALIZE_SCALAR(sec_ctrl_size);
|
|
|
|
UNSERIALIZE_SCALAR(bmi_addr);
|
|
|
|
UNSERIALIZE_SCALAR(bmi_size);
|
|
|
|
|
|
|
|
// Unserialize registers
|
2005-08-23 17:45:52 +02:00
|
|
|
UNSERIALIZE_ARRAY(bmi_regs.data,
|
|
|
|
sizeof(bmi_regs.data) / sizeof(bmi_regs.data[0]));
|
|
|
|
UNSERIALIZE_ARRAY(dev, sizeof(dev) / sizeof(dev[0]));
|
|
|
|
UNSERIALIZE_ARRAY(config_regs.data,
|
|
|
|
sizeof(config_regs.data) / sizeof(config_regs.data[0]));
|
2004-05-12 22:55:49 +02:00
|
|
|
|
|
|
|
// Unserialize internal state
|
|
|
|
UNSERIALIZE_SCALAR(io_enabled);
|
|
|
|
UNSERIALIZE_SCALAR(bm_enabled);
|
2005-08-23 17:45:52 +02:00
|
|
|
UNSERIALIZE_ARRAY(cmd_in_progress,
|
|
|
|
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
|
2006-04-20 23:14:30 +02:00
|
|
|
SimObjectParam<System *> system;
|
|
|
|
SimObjectParam<Platform *> platform;
|
2004-03-23 23:10:07 +01:00
|
|
|
SimObjectParam<PciConfigData *> configdata;
|
|
|
|
Param<uint32_t> pci_bus;
|
|
|
|
Param<uint32_t> pci_dev;
|
|
|
|
Param<uint32_t> pci_func;
|
2004-07-13 04:58:22 +02:00
|
|
|
Param<Tick> pio_latency;
|
2006-07-27 22:43:02 +02:00
|
|
|
Param<Tick> config_latency;
|
2006-04-20 23:14:30 +02:00
|
|
|
SimObjectVectorParam<IdeDisk *> disks;
|
2004-03-23 23:10:07 +01:00
|
|
|
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
|
2006-04-20 23:14:30 +02:00
|
|
|
INIT_PARAM(system, "System pointer"),
|
|
|
|
INIT_PARAM(platform, "Platform pointer"),
|
2004-03-23 23:10:07 +01:00
|
|
|
INIT_PARAM(configdata, "PCI Config data"),
|
|
|
|
INIT_PARAM(pci_bus, "PCI bus ID"),
|
|
|
|
INIT_PARAM(pci_dev, "PCI device number"),
|
|
|
|
INIT_PARAM(pci_func, "PCI function code"),
|
2004-07-13 04:58:22 +02:00
|
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
2006-07-27 22:43:02 +02:00
|
|
|
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
|
2006-04-20 23:14:30 +02:00
|
|
|
INIT_PARAM(disks, "IDE disks attached to this controller")
|
2004-03-23 23:10:07 +01:00
|
|
|
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
|
|
|
|
CREATE_SIM_OBJECT(IdeController)
|
|
|
|
{
|
2004-11-13 21:45:22 +01:00
|
|
|
IdeController::Params *params = new IdeController::Params;
|
|
|
|
params->name = getInstanceName();
|
2006-04-20 23:14:30 +02:00
|
|
|
params->platform = platform;
|
|
|
|
params->system = system;
|
2004-11-13 21:45:22 +01:00
|
|
|
params->configData = configdata;
|
|
|
|
params->busNum = pci_bus;
|
|
|
|
params->deviceNum = pci_dev;
|
|
|
|
params->functionNum = pci_func;
|
2006-04-20 23:14:30 +02:00
|
|
|
params->pio_delay = pio_latency;
|
2006-07-27 22:43:02 +02:00
|
|
|
params->config_delay = config_latency;
|
2004-11-13 21:45:22 +01:00
|
|
|
params->disks = disks;
|
|
|
|
return new IdeController(params);
|
2004-03-23 23:10:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
REGISTER_SIM_OBJECT("IdeController", IdeController)
|
|
|
|
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|