Fixes to DMA writing (still unverified) and added serialize/unserialize
dev/ide_ctrl.cc:
Added serialize/unserialize functions and move some inlined functions
to regular functions
dev/ide_ctrl.hh:
Change inlined functions to regular functions
dev/ide_disk.cc:
Changes to dmaWrite and also add serialize/unserialize functions
dev/ide_disk.hh:
Support for serializing/unserializing
--HG--
extra : convert_revision : 40e016dc7f6637b033fe33409338437c985a05f4
This commit is contained in:
Andrew Schultz
parent
c5ec5bf3a7
commit
ab9415a2bd
108
dev/ide_ctrl.cc
108
dev/ide_ctrl.cc
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@ -126,6 +126,72 @@ IdeController::~IdeController()
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delete disks[i];
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}
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////
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// Utility functions
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///
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void
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IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
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RegType_t &type)
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{
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offset = addr;
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if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
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offset -= pri_cmd_addr;
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type = COMMAND_BLOCK;
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primary = true;
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} else if (addr >= pri_ctrl_addr &&
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addr < (pri_ctrl_addr + pri_ctrl_size)) {
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offset -= pri_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = true;
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} else if (addr >= sec_cmd_addr &&
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addr < (sec_cmd_addr + sec_cmd_size)) {
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offset -= sec_cmd_addr;
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type = COMMAND_BLOCK;
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primary = false;
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} else if (addr >= sec_ctrl_addr &&
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addr < (sec_ctrl_addr + sec_ctrl_size)) {
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offset -= sec_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = false;
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} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
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offset -= bmi_addr;
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type = BMI_BLOCK;
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primary = (offset < BMIC1) ? true : false;
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} else {
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panic("IDE controller access to invalid address: %#x\n", addr);
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}
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}
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int
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IdeController::getDisk(bool primary)
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{
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int disk = 0;
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uint8_t *devBit = &dev[0];
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if (!primary) {
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disk += 2;
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devBit = &dev[1];
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}
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disk += *devBit;
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assert(*devBit == 0 || *devBit == 1);
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return disk;
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}
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int
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IdeController::getDisk(IdeDisk *diskPtr)
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{
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for (int i = 0; i < 4; i++) {
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if ((long)diskPtr == (long)disks[i])
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return i;
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}
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return -1;
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}
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////
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// Command completion
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////
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@ -523,11 +589,53 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
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void
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IdeController::serialize(std::ostream &os)
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{
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// Serialize register addresses and sizes
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SERIALIZE_SCALAR(pri_cmd_addr);
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SERIALIZE_SCALAR(pri_cmd_size);
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SERIALIZE_SCALAR(pri_ctrl_addr);
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SERIALIZE_SCALAR(pri_ctrl_size);
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SERIALIZE_SCALAR(sec_cmd_addr);
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SERIALIZE_SCALAR(sec_cmd_size);
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SERIALIZE_SCALAR(sec_ctrl_addr);
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SERIALIZE_SCALAR(sec_ctrl_size);
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SERIALIZE_SCALAR(bmi_addr);
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SERIALIZE_SCALAR(bmi_size);
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// Serialize registers
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SERIALIZE_ARRAY(bmi_regs, 16);
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SERIALIZE_ARRAY(dev, 2);
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SERIALIZE_ARRAY(pci_regs, 8);
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// Serialize internal state
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SERIALIZE_SCALAR(io_enabled);
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SERIALIZE_SCALAR(bm_enabled);
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SERIALIZE_ARRAY(cmd_in_progress, 4);
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}
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void
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IdeController::unserialize(Checkpoint *cp, const std::string §ion)
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{
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// Unserialize register addresses and sizes
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UNSERIALIZE_SCALAR(pri_cmd_addr);
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UNSERIALIZE_SCALAR(pri_cmd_size);
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UNSERIALIZE_SCALAR(pri_ctrl_addr);
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UNSERIALIZE_SCALAR(pri_ctrl_size);
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UNSERIALIZE_SCALAR(sec_cmd_addr);
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UNSERIALIZE_SCALAR(sec_cmd_size);
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UNSERIALIZE_SCALAR(sec_ctrl_addr);
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UNSERIALIZE_SCALAR(sec_ctrl_size);
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UNSERIALIZE_SCALAR(bmi_addr);
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UNSERIALIZE_SCALAR(bmi_size);
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// Unserialize registers
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UNSERIALIZE_ARRAY(bmi_regs, 16);
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UNSERIALIZE_ARRAY(dev, 2);
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UNSERIALIZE_ARRAY(pci_regs, 8);
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// Unserialize internal state
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UNSERIALIZE_SCALAR(io_enabled);
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UNSERIALIZE_SCALAR(bm_enabled);
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UNSERIALIZE_ARRAY(cmd_in_progress, 4);
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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@ -27,7 +27,8 @@
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*/
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/** @file
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* Simple PCI IDE controller with bus mastering capability
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* Simple PCI IDE controller with bus mastering capability and UDMA
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* modeled after controller in the Intel PIIX4 chip
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*/
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#ifndef __IDE_CTRL_HH__
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@ -139,65 +140,13 @@ class IdeController : public PciDev
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private:
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/** Parse the access address to pass on to device */
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void parseAddr(const Addr &addr, Addr &offset, bool &primary,
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RegType_t &type)
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{
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offset = addr;
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if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
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offset -= pri_cmd_addr;
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type = COMMAND_BLOCK;
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primary = true;
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} else if (addr >= pri_ctrl_addr &&
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addr < (pri_ctrl_addr + pri_ctrl_size)) {
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offset -= pri_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = true;
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} else if (addr >= sec_cmd_addr &&
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addr < (sec_cmd_addr + sec_cmd_size)) {
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offset -= sec_cmd_addr;
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type = COMMAND_BLOCK;
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primary = false;
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} else if (addr >= sec_ctrl_addr &&
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addr < (sec_ctrl_addr + sec_ctrl_size)) {
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offset -= sec_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = false;
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} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
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offset -= bmi_addr;
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type = BMI_BLOCK;
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primary = (offset < BMIC1) ? true : false;
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} else {
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panic("IDE controller access to invalid address: %#x\n", addr);
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}
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};
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RegType_t &type);
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/** Select the disk based on the channel and device bit */
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int getDisk(bool primary)
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{
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int disk = 0;
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uint8_t *devBit = &dev[0];
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if (!primary) {
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disk += 2;
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devBit = &dev[1];
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}
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disk += *devBit;
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assert(*devBit == 0 || *devBit == 1);
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return disk;
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};
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int getDisk(bool primary);
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/** Select the disk based on a pointer */
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int getDisk(IdeDisk *diskPtr)
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{
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for (int i = 0; i < 4; i++) {
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if ((long)diskPtr == (long)disks[i])
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return i;
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}
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return -1;
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}
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int getDisk(IdeDisk *diskPtr);
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public:
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/**
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223
dev/ide_disk.cc
223
dev/ide_disk.cc
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@ -61,6 +61,7 @@ IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
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dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
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dmaReadEvent(this), dmaWriteEvent(this)
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{
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// calculate disk delay in microseconds
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diskDelay = (delay * ticksPerSecond / 100000);
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// initialize the data buffer and shadow registers
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@ -70,6 +71,7 @@ IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
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memset(&cmdReg, 0, sizeof(CommandReg_t));
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memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
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dmaInterfaceBytes = 0;
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curPrdAddr = 0;
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curSector = 0;
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curCommand = 0;
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@ -154,8 +156,12 @@ IdeDisk::~IdeDisk()
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delete [] dataBuffer;
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}
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////
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// Utility functions
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////
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Addr
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IdeDisk::pciToDma(Addr &pciAddr)
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IdeDisk::pciToDma(Addr pciAddr)
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{
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if (ctrl)
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return ctrl->tsunami->pchip->translatePciToDma(pciAddr);
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@ -163,6 +169,29 @@ IdeDisk::pciToDma(Addr &pciAddr)
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panic("Access to unset controller!\n");
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}
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uint32_t
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IdeDisk::bytesInDmaPage(Addr curAddr, uint32_t bytesLeft)
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{
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uint32_t bytesInPage = 0;
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// First calculate how many bytes could be in the page
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if (bytesLeft > ALPHA_PGBYTES)
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bytesInPage = ALPHA_PGBYTES;
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else
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bytesInPage = bytesLeft;
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// Next, see if we have crossed a page boundary, and adjust
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Addr upperBound = curAddr + bytesInPage;
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Addr pageBound = alpha_trunc_page(curAddr) + ALPHA_PGBYTES;
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assert(upperBound >= curAddr && "DMA read wraps around address space!\n");
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if (upperBound >= pageBound)
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bytesInPage = pageBound - curAddr;
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return bytesInPage;
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}
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////
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// Device registers read/write
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////
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@ -297,7 +326,7 @@ IdeDisk::dmaPrdReadDone()
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void
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IdeDisk::doDmaRead()
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{
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Tick totalDiskDelay = diskDelay * (curPrd.getByteCount() / SectorSize);
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Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
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if (dmaInterface) {
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if (dmaInterface->busy()) {
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@ -306,9 +335,14 @@ IdeDisk::doDmaRead()
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return;
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}
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Addr dmaAddr =
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ctrl->tsunami->pchip->translatePciToDma(curPrd.getBaseAddr());
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dmaInterface->doDMA(Read, dmaAddr, curPrd.getByteCount(),
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Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
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uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
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(uint32_t)curPrd.getByteCount());
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dmaInterfaceBytes = bytesInPage;
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dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
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curTick + totalDiskDelay, &dmaReadEvent);
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} else {
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// schedule dmaReadEvent with sectorDelay (dmaReadDone)
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@ -323,6 +357,28 @@ IdeDisk::dmaReadDone()
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Addr curAddr = 0, dmaAddr = 0;
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uint32_t bytesWritten = 0, bytesInPage = 0, bytesLeft = 0;
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// continue to use the DMA interface until all pages are read
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if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
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// see if the interface is busy
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaReadEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
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curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
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dmaAddr = pciToDma(curAddr);
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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dmaInterfaceBytes += bytesInPage;
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dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
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curTick, &dmaReadEvent);
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return;
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}
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// set initial address
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curAddr = curPrd.getBaseAddr();
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@ -338,15 +394,9 @@ IdeDisk::dmaReadDone()
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// calculate how many bytes are in the current page
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bytesLeft = curPrd.getByteCount() - bytesWritten;
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bytesInPage = (bytesLeft > ALPHA_PGBYTES) ? ALPHA_PGBYTES : bytesLeft;
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// check to make sure we don't cross a page boundary
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if ((curAddr + bytesInPage) >
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(alpha_trunc_page(curAddr) + ALPHA_PGBYTES))
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bytesInPage = alpha_round_page(curAddr) - curAddr;
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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// copy the data from memory into the data buffer
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/** @todo Use real DMA with interfaces here */
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memcpy((void *)(dataBuffer + bytesWritten),
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physmem->dma_addr(dmaAddr, bytesInPage),
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bytesInPage);
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@ -359,9 +409,10 @@ IdeDisk::dmaReadDone()
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// write the data to the disk image
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for (bytesWritten = 0;
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bytesWritten < curPrd.getByteCount();
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bytesWritten += SectorSize)
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bytesWritten += SectorSize) {
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writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
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}
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#if 0
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// actually copy the data from memory to data buffer
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@ -397,7 +448,7 @@ IdeDisk::dmaReadDone()
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void
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IdeDisk::doDmaWrite()
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{
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Tick totalDiskDelay = diskDelay * (curPrd.getByteCount() / SectorSize);
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Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
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if (dmaInterface) {
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if (dmaInterface->busy()) {
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@ -406,10 +457,15 @@ IdeDisk::doDmaWrite()
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return;
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}
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Addr dmaAddr =
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ctrl->tsunami->pchip->translatePciToDma(curPrd.getBaseAddr());
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Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
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uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
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(uint32_t)curPrd.getByteCount());
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dmaInterfaceBytes = bytesInPage;
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dmaInterface->doDMA(WriteInvalidate, dmaAddr,
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curPrd.getByteCount(), curTick + totalDiskDelay,
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bytesInPage, curTick + totalDiskDelay,
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&dmaWriteEvent);
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} else {
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// schedule event with disk delay (dmaWriteDone)
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@ -423,6 +479,29 @@ IdeDisk::dmaWriteDone()
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Addr curAddr = 0, pageAddr = 0, dmaAddr = 0;
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uint32_t bytesRead = 0, bytesInPage = 0;
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// continue to use the DMA interface until all pages are read
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if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
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// see if the interface is busy
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if (dmaInterface->busy()) {
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// reschedule after waiting period
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dmaWriteEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
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return;
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}
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uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
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curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
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dmaAddr = pciToDma(curAddr);
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bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
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dmaInterfaceBytes += bytesInPage;
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dmaInterface->doDMA(WriteInvalidate, dmaAddr,
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bytesInPage, curTick,
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&dmaWriteEvent);
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return;
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}
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// setup the initial page and DMA address
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curAddr = curPrd.getBaseAddr();
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pageAddr = alpha_trunc_page(curAddr);
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@ -435,7 +514,6 @@ IdeDisk::dmaWriteDone()
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// see if we have crossed into a new page
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if (pageAddr != alpha_trunc_page(curAddr)) {
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// write the data to memory
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/** @todo Do real DMA using interfaces here */
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memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
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(void *)(dataBuffer + (bytesRead - bytesInPage)),
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bytesInPage);
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@ -459,7 +537,6 @@ IdeDisk::dmaWriteDone()
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}
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// write the last page worth read to memory
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/** @todo Do real DMA using interfaces here */
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if (bytesInPage != 0) {
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memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
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(void *)(dataBuffer + (bytesRead - bytesInPage)),
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@ -521,7 +598,7 @@ IdeDisk::startDma(const uint32_t &prdTableBase)
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if (devState != Transfer_Data_Dma)
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panic("Inconsistent device state for DMA start!\n");
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curPrdAddr = ctrl->tsunami->pchip->translatePciToDma(prdTableBase);
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curPrdAddr = pciToDma((Addr)prdTableBase);
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dmaState = Dma_Transfer;
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@ -927,11 +1004,115 @@ IdeDisk::updateState(DevAction_t action)
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void
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IdeDisk::serialize(ostream &os)
|
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{
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// Check all outstanding events to see if they are scheduled
|
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// these are all mutually exclusive
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Tick reschedule = 0;
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Events_t event = None;
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if (dmaTransferEvent.scheduled()) {
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reschedule = dmaTransferEvent.when();
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event = Transfer;
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} else if (dmaReadWaitEvent.scheduled()) {
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reschedule = dmaReadWaitEvent.when();
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event = ReadWait;
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} else if (dmaWriteWaitEvent.scheduled()) {
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reschedule = dmaWriteWaitEvent.when();
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event = WriteWait;
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} else if (dmaPrdReadEvent.scheduled()) {
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reschedule = dmaPrdReadEvent.when();
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event = PrdRead;
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} else if (dmaReadEvent.scheduled()) {
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reschedule = dmaReadEvent.when();
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event = DmaRead;
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} else if (dmaWriteEvent.scheduled()) {
|
||||
reschedule = dmaWriteEvent.when();
|
||||
event = DmaWrite;
|
||||
}
|
||||
|
||||
SERIALIZE_SCALAR(reschedule);
|
||||
SERIALIZE_ENUM(event);
|
||||
|
||||
// Serialize device registers
|
||||
SERIALIZE_SCALAR(cmdReg.data0);
|
||||
SERIALIZE_SCALAR(cmdReg.data1);
|
||||
SERIALIZE_SCALAR(cmdReg.sec_count);
|
||||
SERIALIZE_SCALAR(cmdReg.sec_num);
|
||||
SERIALIZE_SCALAR(cmdReg.cyl_low);
|
||||
SERIALIZE_SCALAR(cmdReg.cyl_high);
|
||||
SERIALIZE_SCALAR(cmdReg.drive);
|
||||
SERIALIZE_SCALAR(cmdReg.status);
|
||||
SERIALIZE_SCALAR(nIENBit);
|
||||
SERIALIZE_SCALAR(devID);
|
||||
|
||||
// Serialize the PRD related information
|
||||
SERIALIZE_SCALAR(curPrd.entry.baseAddr);
|
||||
SERIALIZE_SCALAR(curPrd.entry.byteCount);
|
||||
SERIALIZE_SCALAR(curPrd.entry.endOfTable);
|
||||
SERIALIZE_SCALAR(curPrdAddr);
|
||||
|
||||
// Serialize current transfer related information
|
||||
SERIALIZE_SCALAR(cmdBytesLeft);
|
||||
SERIALIZE_SCALAR(drqBytesLeft);
|
||||
SERIALIZE_SCALAR(curSector);
|
||||
SERIALIZE_SCALAR(curCommand);
|
||||
SERIALIZE_SCALAR(dmaRead);
|
||||
SERIALIZE_SCALAR(dmaInterfaceBytes);
|
||||
SERIALIZE_SCALAR(intrPending);
|
||||
SERIALIZE_ENUM(devState);
|
||||
SERIALIZE_ENUM(dmaState);
|
||||
SERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
|
||||
}
|
||||
|
||||
void
|
||||
IdeDisk::unserialize(Checkpoint *cp, const string §ion)
|
||||
{
|
||||
// Reschedule events that were outstanding
|
||||
// these are all mutually exclusive
|
||||
Tick reschedule = 0;
|
||||
Events_t event = None;
|
||||
|
||||
UNSERIALIZE_SCALAR(reschedule);
|
||||
UNSERIALIZE_ENUM(event);
|
||||
|
||||
switch (event) {
|
||||
case None : break;
|
||||
case Transfer : dmaTransferEvent.schedule(reschedule); break;
|
||||
case ReadWait : dmaReadWaitEvent.schedule(reschedule); break;
|
||||
case WriteWait : dmaWriteWaitEvent.schedule(reschedule); break;
|
||||
case PrdRead : dmaPrdReadEvent.schedule(reschedule); break;
|
||||
case DmaRead : dmaReadEvent.schedule(reschedule); break;
|
||||
case DmaWrite : dmaWriteEvent.schedule(reschedule); break;
|
||||
}
|
||||
|
||||
// Unserialize device registers
|
||||
UNSERIALIZE_SCALAR(cmdReg.data0);
|
||||
UNSERIALIZE_SCALAR(cmdReg.data1);
|
||||
UNSERIALIZE_SCALAR(cmdReg.sec_count);
|
||||
UNSERIALIZE_SCALAR(cmdReg.sec_num);
|
||||
UNSERIALIZE_SCALAR(cmdReg.cyl_low);
|
||||
UNSERIALIZE_SCALAR(cmdReg.cyl_high);
|
||||
UNSERIALIZE_SCALAR(cmdReg.drive);
|
||||
UNSERIALIZE_SCALAR(cmdReg.status);
|
||||
UNSERIALIZE_SCALAR(nIENBit);
|
||||
UNSERIALIZE_SCALAR(devID);
|
||||
|
||||
// Unserialize the PRD related information
|
||||
UNSERIALIZE_SCALAR(curPrd.entry.baseAddr);
|
||||
UNSERIALIZE_SCALAR(curPrd.entry.byteCount);
|
||||
UNSERIALIZE_SCALAR(curPrd.entry.endOfTable);
|
||||
UNSERIALIZE_SCALAR(curPrdAddr);
|
||||
|
||||
// Unserialize current transfer related information
|
||||
UNSERIALIZE_SCALAR(cmdBytesLeft);
|
||||
UNSERIALIZE_SCALAR(drqBytesLeft);
|
||||
UNSERIALIZE_SCALAR(curSector);
|
||||
UNSERIALIZE_SCALAR(curCommand);
|
||||
UNSERIALIZE_SCALAR(dmaRead);
|
||||
UNSERIALIZE_SCALAR(dmaInterfaceBytes);
|
||||
UNSERIALIZE_SCALAR(intrPending);
|
||||
UNSERIALIZE_ENUM(devState);
|
||||
UNSERIALIZE_ENUM(dmaState);
|
||||
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
|
||||
}
|
||||
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
|
@ -950,7 +1131,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
|||
INIT_PARAM(image, "Disk image"),
|
||||
INIT_PARAM(physmem, "Physical memory"),
|
||||
INIT_PARAM(driveID, "Drive ID (0=master 1=slave)"),
|
||||
INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in milliseconds", 0)
|
||||
INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in microseconds", 1)
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
||||
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ class PrdTableEntry {
|
|||
#define STATUS_BSY_BIT 0x80
|
||||
#define STATUS_DRDY_BIT 0x40
|
||||
#define STATUS_DRQ_BIT 0x08
|
||||
#define DRIVE_LBA_BIT 0x40
|
||||
#define DRIVE_LBA_BIT 0x40
|
||||
|
||||
#define DEV0 (0)
|
||||
#define DEV1 (1)
|
||||
|
|
@ -120,6 +120,16 @@ typedef struct CommandReg {
|
|||
};
|
||||
} CommandReg_t;
|
||||
|
||||
typedef enum Events {
|
||||
None = 0,
|
||||
Transfer,
|
||||
ReadWait,
|
||||
WriteWait,
|
||||
PrdRead,
|
||||
DmaRead,
|
||||
DmaWrite
|
||||
} Events_t;
|
||||
|
||||
typedef enum DevAction {
|
||||
ACT_NONE = 0,
|
||||
ACT_CMD_WRITE,
|
||||
|
|
@ -184,7 +194,7 @@ class IdeDisk : public SimObject
|
|||
PhysicalMemory *physmem;
|
||||
|
||||
protected:
|
||||
/** The disk delay in milliseconds. */
|
||||
/** The disk delay in microseconds. */
|
||||
int diskDelay;
|
||||
|
||||
private:
|
||||
|
|
@ -214,6 +224,8 @@ class IdeDisk : public SimObject
|
|||
uint32_t curPrdAddr;
|
||||
/** PRD entry */
|
||||
PrdTableEntry curPrd;
|
||||
/** Number of bytes transfered by DMA interface for current transfer */
|
||||
uint32_t dmaInterfaceBytes;
|
||||
/** Device ID (master=0/slave=1) */
|
||||
int devID;
|
||||
/** Interrupt pending */
|
||||
|
|
@ -313,7 +325,9 @@ class IdeDisk : public SimObject
|
|||
(cmdReg.cyl_low << 8) | (cmdReg.sec_num));
|
||||
}
|
||||
|
||||
inline Addr pciToDma(Addr &pciAddr);
|
||||
inline Addr pciToDma(Addr pciAddr);
|
||||
|
||||
uint32_t bytesInDmaPage(Addr curAddr, uint32_t bytesLeft);
|
||||
|
||||
/**
|
||||
* Serialize this object to the given output stream.
|
||||
|
|
|
|||
Loading…
Reference in a new issue