gem5/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                1898996                       # Simulator instruction rate (inst/s)
host_mem_usage                                 207084                       # Number of bytes of host memory used
host_seconds                                   784.37                       # Real time elapsed on the host
host_tick_rate                             2646697045                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                  1489523295                       # Number of instructions simulated
sim_seconds                                  2.076001                       # Number of seconds simulated
sim_ticks                                2076000877000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses          402512844                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              402319358                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     4079726000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000481                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses               193486                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency   3499268000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000481                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses          193486                       # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits                   1286                       # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency        2240000                       # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate          0.030166                       # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses                   40                       # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency      2120000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate     0.030166                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses              40                       # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits             166527221                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   17897318000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.001915                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              319595                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency  16938533000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.001915                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         319595                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           569359660                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 42833.478535                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               568846579                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     21977044000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000901                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                513081                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  20437801000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000901                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           513081                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42833.478535                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              568846579                       # number of overall hits
system.cpu.dcache.overall_miss_latency    21977044000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000901                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               513081                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  20437801000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000901                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          513081                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 449125                       # number of replacements
system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4095.229973                       # Cycle average of tags in use
system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle              567696000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   316424                       # number of writebacks
system.cpu.icache.ReadReq_accesses         1485113012                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits             1485111905                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       61824000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 1107                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency     58503000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            1107                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses          1485113012                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55848.238482                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
system.cpu.icache.demand_hits              1485111905                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        61824000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  1107                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     58503000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             1107                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits             1485111905                       # number of overall hits
system.cpu.icache.overall_miss_latency       61824000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 1107                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     58503000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            1107                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                    118                       # number of replacements
system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                906.413760                       # Cycle average of tags in use
system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses          259735                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency  13506220000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            259735                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency  10389400000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       259735                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            194593                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                160849                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    1754688000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.173408                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               33744                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1349760000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.173408                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          33744                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses          59900                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency   3114696000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses            59900                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2396000000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses        59900                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses          316424                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              316424                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  3.428657                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             454328                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 160849                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency    15260908000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.645963                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               293479                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency  11739160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.645963                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          293479                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                160849                       # number of overall hits
system.cpu.l2cache.overall_miss_latency   15260908000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.645963                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              293479                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency  11739160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.645963                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         293479                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                 82908                       # number of replacements
system.cpu.l2cache.sampled_refs                 98342                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             16358.086686                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  337181                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   61864                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                       4152001754                       # number of cpu cycles simulated
system.cpu.num_insts                       1489523295                       # Number of instructions executed
system.cpu.num_refs                         569365767                       # Number of memory references
system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls

---------- End Simulation Statistics   ----------