2006-05-16 19:59:29 +02:00
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/*
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2006-05-23 22:59:13 +02:00
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* Copyright (c) 2006 The Regents of The University of Michigan
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2006-05-16 19:59:29 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <list>
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#include <string>
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#include "base/refcnt.hh"
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#include "cpu/base.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/static_inst.hh"
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#include "sim/byteswap.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "cpu/ozone/dyn_inst.hh"
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#include "cpu/ozone/ozone_impl.hh"
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#include "cpu/ozone/simple_impl.hh"
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#if FULL_SYSTEM
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#include "sim/system.hh"
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#include "arch/vtophys.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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//The CheckerCPU does alpha only
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using namespace AlphaISA;
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void
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CheckerCPU::init()
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{
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}
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CheckerCPU::CheckerCPU(Params *p)
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: BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
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{
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memReq = new MemReq();
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memReq->xc = xcProxy;
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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youngestSN = 0;
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changedPC = willChangePC = changedNextPC = false;
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exitOnError = p->exitOnError;
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2006-08-02 18:06:59 +02:00
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updateOnError = p->updateOnError;
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2006-05-16 19:59:29 +02:00
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#if FULL_SYSTEM
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itb = p->itb;
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dtb = p->dtb;
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systemPtr = NULL;
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memPtr = NULL;
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#endif
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}
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CheckerCPU::~CheckerCPU()
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{
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}
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void
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CheckerCPU::setMemory(FunctionalMemory *mem)
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{
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memPtr = mem;
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#if !FULL_SYSTEM
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, mem,
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/* asid */ 0);
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cpuXC->setStatus(ExecContext::Suspended);
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xcProxy = cpuXC->getProxy();
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execContexts.push_back(xcProxy);
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#else
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if (systemPtr) {
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2006-05-25 17:50:42 +02:00
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cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
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2006-05-16 19:59:29 +02:00
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cpuXC->setStatus(ExecContext::Suspended);
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xcProxy = cpuXC->getProxy();
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execContexts.push_back(xcProxy);
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memReq->xc = xcProxy;
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2006-05-23 22:59:13 +02:00
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delete cpuXC->kernelStats;
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cpuXC->kernelStats = NULL;
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2006-05-16 19:59:29 +02:00
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}
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#endif
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}
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#if FULL_SYSTEM
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void
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CheckerCPU::setSystem(System *system)
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{
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systemPtr = system;
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if (memPtr) {
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2006-05-25 17:50:42 +02:00
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cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
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2006-05-16 19:59:29 +02:00
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cpuXC->setStatus(ExecContext::Suspended);
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xcProxy = cpuXC->getProxy();
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execContexts.push_back(xcProxy);
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memReq->xc = xcProxy;
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2006-05-23 22:59:13 +02:00
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delete cpuXC->kernelStats;
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cpuXC->kernelStats = NULL;
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2006-05-16 19:59:29 +02:00
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}
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}
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#endif
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void
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CheckerCPU::serialize(ostream &os)
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{
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/*
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BaseCPU::serialize(os);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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cpuXC->serialize(os);
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cacheCompletionEvent.serialize(os);
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*/
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}
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void
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CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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/*
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_SCALAR(inst);
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cpuXC->unserialize(cp, csprintf("%s.xc", section));
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*/
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}
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Fault
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CheckerCPU::copySrcTranslate(Addr src)
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{
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2006-05-23 22:59:13 +02:00
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panic("Unimplemented!");
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2006-05-16 19:59:29 +02:00
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}
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Fault
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CheckerCPU::copy(Addr dest)
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{
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2006-05-23 22:59:13 +02:00
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panic("Unimplemented!");
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2006-05-16 19:59:29 +02:00
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}
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template <class T>
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Fault
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CheckerCPU::read(Addr addr, T &data, unsigned flags)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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translateDataReadReq(memReq);
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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if (!(memReq->flags & UNCACHEABLE)) {
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2006-05-23 22:59:13 +02:00
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// Access memory to see if we have the same data
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2006-05-16 19:59:29 +02:00
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cpuXC->read(memReq, data);
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} else {
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// Assume the data is correct if it's an uncached access
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memcpy(&data, &unverifiedResult.integer, sizeof(T));
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}
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return NoFault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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CheckerCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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CheckerCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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cpuXC->translateDataWriteReq(memReq);
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2006-05-23 22:59:13 +02:00
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// Can compare the write data and result only if it's cacheable,
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// not a store conditional, or is a store conditional that
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// succeeded.
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// @todo: Verify that actual memory matches up with these values.
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// Right now it only verifies that the instruction data is the
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// same as what was in the request that got sent to memory; there
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// is no verification that it is the same as what is in memory.
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// This is because the LSQ would have to be snooped in the CPU to
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// verify this data.
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if (unverifiedReq &&
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!(unverifiedReq->flags & UNCACHEABLE) &&
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(!(unverifiedReq->flags & LOCKED) ||
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((unverifiedReq->flags & LOCKED) &&
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unverifiedReq->result == 1))) {
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#if 0
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memReq->cmd = Read;
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2006-05-16 19:59:29 +02:00
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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2006-05-23 22:59:13 +02:00
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cpuXC->read(memReq, inst_data);
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#endif
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T inst_data;
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memcpy(&inst_data, unverifiedReq->data, sizeof(T));
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2006-05-16 19:59:29 +02:00
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if (data != inst_data) {
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2006-05-23 22:59:13 +02:00
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warn("%lli: Store value does not match value in memory! "
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2006-05-16 19:59:29 +02:00
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"Instruction: %#x, memory: %#x",
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2006-05-23 22:59:13 +02:00
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curTick, inst_data, data);
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2006-05-16 19:59:29 +02:00
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handleError();
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}
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}
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// Assume the result was the same as the one passed in. This checker
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// doesn't check if the SC should succeed or fail, it just checks the
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// value.
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if (res)
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*res = unverifiedReq->result;
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return NoFault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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#if FULL_SYSTEM
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Addr
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CheckerCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(xcProxy, addr);
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}
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#endif // FULL_SYSTEM
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bool
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CheckerCPU::translateInstReq(MemReqPtr &req)
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{
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#if FULL_SYSTEM
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return (cpuXC->translateInstReq(req) == NoFault);
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#else
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cpuXC->translateInstReq(req);
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return true;
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#endif
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}
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void
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CheckerCPU::translateDataReadReq(MemReqPtr &req)
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{
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cpuXC->translateDataReadReq(req);
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2006-08-02 18:06:59 +02:00
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if (!unverifiedReq) {
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warn("%lli: Request virtual addresses do not match! Inst: N/A, "
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"checker: %#x",
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curTick, req->vaddr);
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return;
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} else if (req->vaddr != unverifiedReq->vaddr) {
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2006-05-23 22:59:13 +02:00
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warn("%lli: Request virtual addresses do not match! Inst: %#x, "
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"checker: %#x",
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curTick, unverifiedReq->vaddr, req->vaddr);
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handleError();
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2006-05-16 19:59:29 +02:00
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}
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req->paddr = unverifiedReq->paddr;
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if (checkFlags(req)) {
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2006-05-23 22:59:13 +02:00
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warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
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curTick, unverifiedReq->flags, req->flags);
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2006-05-16 19:59:29 +02:00
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handleError();
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}
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}
|
|
|
|
|
|
|
|
void
|
|
|
|
CheckerCPU::translateDataWriteReq(MemReqPtr &req)
|
|
|
|
{
|
|
|
|
cpuXC->translateDataWriteReq(req);
|
|
|
|
|
2006-08-02 18:06:59 +02:00
|
|
|
if (!unverifiedReq) {
|
|
|
|
warn("%lli: Request virtual addresses do not match! Inst: N/A, "
|
|
|
|
"checker: %#x",
|
|
|
|
curTick, req->vaddr);
|
|
|
|
return;
|
|
|
|
} else if (req->vaddr != unverifiedReq->vaddr) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
|
|
|
|
"checker: %#x",
|
|
|
|
curTick, unverifiedReq->vaddr, req->vaddr);
|
|
|
|
handleError();
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
req->paddr = unverifiedReq->paddr;
|
|
|
|
|
|
|
|
if (checkFlags(req)) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
|
|
|
|
curTick, unverifiedReq->flags, req->flags);
|
2006-05-16 19:59:29 +02:00
|
|
|
handleError();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
CheckerCPU::checkFlags(MemReqPtr &req)
|
|
|
|
{
|
|
|
|
// Remove any dynamic flags that don't have to do with the request itself.
|
|
|
|
unsigned flags = unverifiedReq->flags;
|
|
|
|
unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
|
|
|
|
flags = flags & (mask);
|
|
|
|
if (flags == req->flags) {
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-08-24 23:22:31 +02:00
|
|
|
void
|
|
|
|
CheckerCPU::dumpAndExit()
|
|
|
|
{
|
|
|
|
warn("%lli: Checker PC:%#x, next PC:%#x",
|
|
|
|
curTick, cpuXC->readPC(), cpuXC->readNextPC());
|
|
|
|
panic("Checker found an error!");
|
|
|
|
}
|
|
|
|
|
2006-05-16 19:59:29 +02:00
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
|
|
|
|
{
|
|
|
|
DynInstPtr inst;
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// Either check this instruction, or add it to a list of
|
|
|
|
// instructions waiting to be checked. Instructions must be
|
|
|
|
// checked in program order, so if a store has committed yet not
|
|
|
|
// completed, there may be some instructions that are waiting
|
|
|
|
// behind it that have completed and must be checked.
|
2006-05-16 19:59:29 +02:00
|
|
|
if (!instList.empty()) {
|
|
|
|
if (youngestSN < completed_inst->seqNum) {
|
|
|
|
DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
|
|
|
|
completed_inst->seqNum, completed_inst->readPC());
|
|
|
|
instList.push_back(completed_inst);
|
|
|
|
youngestSN = completed_inst->seqNum;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!instList.front()->isCompleted()) {
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
inst = instList.front();
|
|
|
|
instList.pop_front();
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!completed_inst->isCompleted()) {
|
|
|
|
if (youngestSN < completed_inst->seqNum) {
|
|
|
|
DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
|
|
|
|
completed_inst->seqNum, completed_inst->readPC());
|
|
|
|
instList.push_back(completed_inst);
|
|
|
|
youngestSN = completed_inst->seqNum;
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
if (youngestSN < completed_inst->seqNum) {
|
|
|
|
inst = completed_inst;
|
|
|
|
youngestSN = completed_inst->seqNum;
|
|
|
|
} else {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-08-02 18:06:59 +02:00
|
|
|
unverifiedInst = inst;
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// Try to check all instructions that are completed, ending if we
|
|
|
|
// run out of instructions to check or if an instruction is not
|
|
|
|
// yet completed.
|
2006-05-16 19:59:29 +02:00
|
|
|
while (1) {
|
|
|
|
DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
|
|
|
|
inst->seqNum, inst->readPC());
|
|
|
|
unverifiedResult.integer = inst->readIntResult();
|
|
|
|
unverifiedReq = inst->req;
|
|
|
|
numCycles++;
|
|
|
|
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
// maintain $r0 semantics
|
|
|
|
cpuXC->setIntReg(ZeroReg, 0);
|
|
|
|
#ifdef TARGET_ALPHA
|
|
|
|
cpuXC->setFloatRegDouble(ZeroReg, 0.0);
|
|
|
|
#endif // TARGET_ALPHA
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// Check if any recent PC changes match up with anything we
|
|
|
|
// expect to happen. This is mostly to check if traps or
|
|
|
|
// PC-based events have occurred in both the checker and CPU.
|
2006-05-16 19:59:29 +02:00
|
|
|
if (changedPC) {
|
|
|
|
DPRINTF(Checker, "Changed PC recently to %#x\n",
|
|
|
|
cpuXC->readPC());
|
|
|
|
if (willChangePC) {
|
|
|
|
if (newPC == cpuXC->readPC()) {
|
|
|
|
DPRINTF(Checker, "Changed PC matches expected PC\n");
|
|
|
|
} else {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Changed PC does not match expected PC, "
|
|
|
|
"changed: %#x, expected: %#x",
|
|
|
|
curTick, cpuXC->readPC(), newPC);
|
2006-08-24 23:22:31 +02:00
|
|
|
CheckerCPU::handleError();
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
willChangePC = false;
|
|
|
|
}
|
|
|
|
changedPC = false;
|
|
|
|
}
|
|
|
|
if (changedNextPC) {
|
|
|
|
DPRINTF(Checker, "Changed NextPC recently to %#x\n",
|
|
|
|
cpuXC->readNextPC());
|
|
|
|
changedNextPC = false;
|
|
|
|
}
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// Try to fetch the instruction
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
|
|
#else
|
|
|
|
#define IFETCH_FLAGS(pc) 0
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// set up memory request for instruction fetch
|
2006-05-16 19:59:29 +02:00
|
|
|
memReq->cmd = Read;
|
|
|
|
memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t),
|
|
|
|
IFETCH_FLAGS(cpuXC->readPC()));
|
|
|
|
|
|
|
|
bool succeeded = translateInstReq(memReq);
|
|
|
|
|
|
|
|
if (!succeeded) {
|
2006-05-17 20:25:10 +02:00
|
|
|
if (inst->getFault() == NoFault) {
|
2006-05-23 22:59:13 +02:00
|
|
|
// In this case the instruction was not a dummy
|
|
|
|
// instruction carrying an ITB fault. In the single
|
|
|
|
// threaded case the ITB should still be able to
|
|
|
|
// translate this instruction; in the SMT case it's
|
|
|
|
// possible that its ITB entry was kicked out.
|
|
|
|
warn("%lli: Instruction PC %#x was not found in the ITB!",
|
|
|
|
curTick, cpuXC->readPC());
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
|
2006-05-17 20:25:10 +02:00
|
|
|
// go to the next instruction
|
|
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
|
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
2006-05-16 19:59:29 +02:00
|
|
|
|
2006-08-02 18:06:59 +02:00
|
|
|
break;
|
2006-05-17 20:25:10 +02:00
|
|
|
} else {
|
2006-05-23 22:59:13 +02:00
|
|
|
// The instruction is carrying an ITB fault. Handle
|
|
|
|
// the fault and see if our results match the CPU on
|
|
|
|
// the next tick().
|
2006-05-17 20:25:10 +02:00
|
|
|
fault = inst->getFault();
|
|
|
|
}
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
|
2006-05-17 20:25:10 +02:00
|
|
|
if (fault == NoFault) {
|
|
|
|
cpuXC->mem->read(memReq, machInst);
|
2006-05-16 19:59:29 +02:00
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// keep an instruction count
|
2006-05-17 20:25:10 +02:00
|
|
|
numInst++;
|
2006-05-16 19:59:29 +02:00
|
|
|
|
2006-05-17 20:25:10 +02:00
|
|
|
// decode the instruction
|
|
|
|
machInst = gtoh(machInst);
|
|
|
|
// Checks that the instruction matches what we expected it to be.
|
|
|
|
// Checks both the machine instruction and the PC.
|
|
|
|
validateInst(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
curStaticInst = StaticInst::decode(makeExtMI(machInst,
|
|
|
|
cpuXC->readPC()));
|
2006-05-16 19:59:29 +02:00
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
2006-05-17 20:25:10 +02:00
|
|
|
cpuXC->setInst(machInst);
|
2006-05-16 19:59:29 +02:00
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
|
2006-05-17 20:25:10 +02:00
|
|
|
fault = inst->getFault();
|
|
|
|
}
|
2006-05-16 19:59:29 +02:00
|
|
|
|
|
|
|
// Either the instruction was a fault and we should process the fault,
|
|
|
|
// or we should just go ahead execute the instruction. This assumes
|
|
|
|
// that the instruction is properly marked as a fault.
|
|
|
|
if (fault == NoFault) {
|
|
|
|
|
|
|
|
cpuXC->func_exe_inst++;
|
|
|
|
|
2006-08-02 18:06:59 +02:00
|
|
|
if (!inst->isUnverifiable())
|
|
|
|
fault = curStaticInst->execute(this, NULL);
|
2006-05-16 19:59:29 +02:00
|
|
|
|
|
|
|
// Checks to make sure instrution results are correct.
|
|
|
|
validateExecution(inst);
|
|
|
|
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
|
|
++numLoad;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (fault != NoFault) {
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
fault->invoke(xcProxy);
|
|
|
|
willChangePC = true;
|
|
|
|
newPC = cpuXC->readPC();
|
|
|
|
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
|
|
|
|
#else // !FULL_SYSTEM
|
|
|
|
fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
} else {
|
|
|
|
#if THE_ISA != MIPS_ISA
|
|
|
|
// go to the next instruction
|
|
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
|
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
|
|
|
#else
|
|
|
|
// go to the next instruction
|
|
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
|
|
cpuXC->setNextPC(cpuXC->readNextNPC());
|
|
|
|
cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
|
|
|
|
#endif
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
2006-05-23 22:59:13 +02:00
|
|
|
// @todo: Determine if these should happen only if the
|
|
|
|
// instruction hasn't faulted. In the SimpleCPU case this may
|
|
|
|
// not be true, but in the O3 or Ozone case this may be true.
|
2006-05-16 19:59:29 +02:00
|
|
|
Addr oldpc;
|
|
|
|
int count = 0;
|
|
|
|
do {
|
|
|
|
oldpc = cpuXC->readPC();
|
|
|
|
system->pcEventQueue.service(xcProxy);
|
|
|
|
count++;
|
|
|
|
} while (oldpc != cpuXC->readPC());
|
|
|
|
if (count > 1) {
|
|
|
|
willChangePC = true;
|
|
|
|
newPC = cpuXC->readPC();
|
|
|
|
DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// @todo: Optionally can check all registers. (Or just those
|
2006-05-16 19:59:29 +02:00
|
|
|
// that have been modified).
|
|
|
|
validateState();
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
// Continue verifying instructions if there's another completed
|
|
|
|
// instruction waiting to be verified.
|
2006-05-16 19:59:29 +02:00
|
|
|
if (instList.empty()) {
|
|
|
|
break;
|
|
|
|
} else if (instList.front()->isCompleted()) {
|
|
|
|
inst = instList.front();
|
|
|
|
instList.pop_front();
|
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-08-02 18:06:59 +02:00
|
|
|
unverifiedInst = NULL;
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::switchOut(Sampler *s)
|
|
|
|
{
|
|
|
|
instList.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
|
|
|
|
{
|
|
|
|
if (inst->readPC() != cpuXC->readPC()) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
|
|
|
|
curTick, inst->readPC(), cpuXC->readPC());
|
2006-05-16 19:59:29 +02:00
|
|
|
if (changedPC) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Changed PCs recently, may not be an error",
|
|
|
|
curTick);
|
2006-05-16 19:59:29 +02:00
|
|
|
} else {
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-23 22:59:13 +02:00
|
|
|
MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
|
|
|
|
|
|
|
|
if (mi != machInst) {
|
|
|
|
warn("%lli: Binary instructions do not match! Inst: %#x, "
|
|
|
|
"checker: %#x",
|
|
|
|
curTick, mi, machInst);
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
|
|
|
|
{
|
|
|
|
if (inst->numDestRegs()) {
|
2006-05-23 22:59:13 +02:00
|
|
|
// @todo: Support more destination registers.
|
2006-05-16 19:59:29 +02:00
|
|
|
if (inst->isUnverifiable()) {
|
2006-05-23 22:59:13 +02:00
|
|
|
// Unverifiable instructions assume they were executed
|
|
|
|
// properly by the CPU. Grab the result from the
|
|
|
|
// instruction and write it to the register.
|
2006-05-16 19:59:29 +02:00
|
|
|
RegIndex idx = inst->destRegIdx(0);
|
|
|
|
if (idx < TheISA::FP_Base_DepTag) {
|
|
|
|
cpuXC->setIntReg(idx, inst->readIntResult());
|
|
|
|
} else if (idx < TheISA::Fpcr_DepTag) {
|
|
|
|
cpuXC->setFloatRegInt(idx, inst->readIntResult());
|
|
|
|
} else {
|
|
|
|
cpuXC->setMiscReg(idx, inst->readIntResult());
|
|
|
|
}
|
|
|
|
} else if (result.integer != inst->readIntResult()) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Instruction results do not match! (Results may not "
|
|
|
|
"actually be integers) Inst: %#x, checker: %#x",
|
|
|
|
curTick, inst->readIntResult(), result.integer);
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (inst->readNextPC() != cpuXC->readNextPC()) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
|
|
|
|
"checker: %#x",
|
|
|
|
curTick, inst->readNextPC(), cpuXC->readNextPC());
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Checking side effect registers can be difficult if they are not
|
|
|
|
// checked simultaneously with the execution of the instruction.
|
|
|
|
// This is because other valid instructions may have modified
|
|
|
|
// these registers in the meantime, and their values are not
|
|
|
|
// stored within the DynInst.
|
|
|
|
while (!miscRegIdxs.empty()) {
|
|
|
|
int misc_reg_idx = miscRegIdxs.front();
|
|
|
|
miscRegIdxs.pop();
|
|
|
|
|
|
|
|
if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
|
|
|
|
cpuXC->readMiscReg(misc_reg_idx)) {
|
2006-05-23 22:59:13 +02:00
|
|
|
warn("%lli: Misc reg idx %i (side effect) does not match! "
|
|
|
|
"Inst: %#x, checker: %#x",
|
|
|
|
curTick, misc_reg_idx,
|
|
|
|
inst->xcBase()->readMiscReg(misc_reg_idx),
|
2006-05-16 19:59:29 +02:00
|
|
|
cpuXC->readMiscReg(misc_reg_idx));
|
2006-08-24 23:22:31 +02:00
|
|
|
handleError(inst);
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::validateState()
|
|
|
|
{
|
2006-08-02 18:06:59 +02:00
|
|
|
if (updateThisCycle) {
|
|
|
|
warn("%lli: Instruction PC %#x results didn't match up, copying all "
|
2006-08-11 23:42:59 +02:00
|
|
|
"registers from main CPU", curTick, unverifiedInst->readPC());
|
2006-08-02 18:06:59 +02:00
|
|
|
// Heavy-weight copying of all registers
|
|
|
|
cpuXC->copyArchRegs(unverifiedInst->xcBase());
|
2006-08-11 23:42:59 +02:00
|
|
|
// Also advance the PC. Hopefully no PC-based events happened.
|
|
|
|
#if THE_ISA != MIPS_ISA
|
|
|
|
// go to the next instruction
|
|
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
|
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
|
|
|
#else
|
|
|
|
// go to the next instruction
|
|
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
|
|
cpuXC->setNextPC(cpuXC->readNextNPC());
|
|
|
|
cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
|
|
|
|
#endif
|
2006-08-02 18:06:59 +02:00
|
|
|
updateThisCycle = false;
|
|
|
|
}
|
2006-05-16 19:59:29 +02:00
|
|
|
}
|
|
|
|
|
2006-08-24 23:22:31 +02:00
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
|
|
|
|
{
|
|
|
|
cprintf("Error detected, instruction information:\n");
|
|
|
|
cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
|
|
"Completed:%i\n",
|
|
|
|
inst->readPC(),
|
|
|
|
inst->readNextPC(),
|
|
|
|
inst->seqNum,
|
|
|
|
inst->threadNumber,
|
|
|
|
inst->isCompleted());
|
|
|
|
inst->dump();
|
|
|
|
CheckerCPU::dumpAndExit();
|
|
|
|
}
|
|
|
|
|
2006-05-16 19:59:29 +02:00
|
|
|
template <class DynInstPtr>
|
|
|
|
void
|
|
|
|
Checker<DynInstPtr>::dumpInsts()
|
|
|
|
{
|
|
|
|
int num = 0;
|
|
|
|
|
|
|
|
InstListIt inst_list_it = --(instList.end());
|
|
|
|
|
|
|
|
cprintf("Inst list size: %i\n", instList.size());
|
|
|
|
|
|
|
|
while (inst_list_it != instList.end())
|
|
|
|
{
|
|
|
|
cprintf("Instruction:%i\n",
|
|
|
|
num);
|
|
|
|
|
|
|
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
|
|
"Completed:%i\n",
|
|
|
|
(*inst_list_it)->readPC(),
|
|
|
|
(*inst_list_it)->seqNum,
|
|
|
|
(*inst_list_it)->threadNumber,
|
|
|
|
(*inst_list_it)->isCompleted());
|
|
|
|
|
|
|
|
cprintf("\n");
|
|
|
|
|
|
|
|
inst_list_it--;
|
|
|
|
++num;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
template
|
|
|
|
class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
|
|
|
|
|
|
|
|
template
|
|
|
|
class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
|