2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.099832 # Number of seconds simulated
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sim_ticks 99831779000 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 87193 # Simulator instruction rate (inst/s)
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host_tick_rate 39323014 # Simulator tick rate (ticks/s)
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host_mem_usage 268152 # Number of bytes of host memory used
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host_seconds 2538.76 # Real time elapsed on the host
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2011-02-05 09:16:09 +01:00
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sim_insts 221363017 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 400 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 199663559 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 26033375 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 26033375 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 2892272 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 23801635 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 21124617 # Number of BTB hits
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.icacheStallCycles 31432261 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 264493397 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 26033375 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 21124617 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 71518034 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 27440776 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 72430048 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 173 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1577 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 29258071 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 583239 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 199575786 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.208704 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.313982 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 129959453 65.12% 65.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4150455 2.08% 67.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 3286315 1.65% 68.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4425223 2.22% 71.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 4327377 2.17% 73.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4568651 2.29% 75.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5572926 2.79% 78.31% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3068408 1.54% 79.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 40216978 20.15% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 199575786 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.130386 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.324695 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 45674333 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 62083287 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 57427578 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 10196895 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 24193693 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 428380569 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 24193693 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 54435501 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 16645801 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 21737 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 58104790 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 46174264 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 415835044 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 22459451 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 21291992 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 441873091 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 1077088979 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1065665407 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 11423572 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.UndoneMaps 207509682 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1829 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1823 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 98204521 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 105334480 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 37821412 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 75455534 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 24783352 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 400833570 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 1827 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 286380326 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 245766 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 179000562 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 366769994 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 581 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 199575786 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.434945 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.451491 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 64436357 32.29% 32.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 57784347 28.95% 61.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 35429830 17.75% 78.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 21049464 10.55% 89.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 13197205 6.61% 96.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 5079102 2.54% 98.70% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1923482 0.96% 99.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 545287 0.27% 99.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 130712 0.07% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 199575786 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 94614 3.23% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 2515029 85.77% 88.99% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 322713 11.01% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 1207901 0.42% 0.42% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 187612443 65.51% 65.93% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.93% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.93% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 1650340 0.58% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 71566969 24.99% 91.50% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 24342673 8.50% 100.00% # Type of FU issued
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::total 286380326 # Type of FU issued
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system.cpu.iq.rate 1.434314 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2932356 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010239 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 770019302 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 574569480 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 277218966 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 5495258 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 5820238 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2640122 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 285339093 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 2765688 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 17496370 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 48684890 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 26476 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 567154 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 17305696 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 45677 # Number of loads that were rescheduled
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 24193693 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 457791 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 303468 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 400835397 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 134633 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 105334480 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 37821412 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1827 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 212810 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 14667 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 567154 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 2502429 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 590366 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3092795 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 282646911 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 70091222 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 3733415 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_refs 93958027 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 15691329 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 23866805 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.415616 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 281113586 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 279859088 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 226653177 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 377782482 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.401653 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.599957 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 179482154 # The number of squashed insts skipped by commit
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branchMispredicts 2892451 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 175382093 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.262176 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.674972 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 66614816 37.98% 37.98% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 64778126 36.94% 74.92% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 16236292 9.26% 84.18% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12183178 6.95% 91.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 5701402 3.25% 94.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 3006065 1.71% 96.09% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 2037233 1.16% 97.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1096406 0.63% 97.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 3728575 2.13% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 175382093 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.count 221363017 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 77165306 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 56649590 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 12326943 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 3728575 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 572498689 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 825932723 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 87773 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.cpi 0.901973 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.901973 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.108680 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.108680 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 526429192 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 287807377 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 3610412 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2295659 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 148624711 # number of misc regfile reads
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.replacements 4242 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1597.360420 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 29250473 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 6209 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 4710.979707 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1597.360420 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.779961 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 29250474 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 29250474 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 29250474 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 7597 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 7597 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 7597 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 175067500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 175067500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 175067500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 29258071 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 29258071 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 29258071 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 23044.293800 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 23044.293800 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 23044.293800 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1135 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1135 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1135 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 6462 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 6462 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 6462 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 125815000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 125815000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 125815000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19469.978335 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 58 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 1414.389130 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 72873832 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1985 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 36712.257935 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 1414.389130 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.345310 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 52365835 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 20507475 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 72873310 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 72873310 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 884 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 8255 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 9139 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 9139 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 27524500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 227342500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 254867000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 254867000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 52366719 # number of ReadReq accesses(hits+misses)
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_accesses 72882449 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 72882449 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 31136.312217 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 27539.975772 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 27887.843309 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 27887.843309 # average overall miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 14 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 460 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 6439 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 6899 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 6899 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1816 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14073500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 63530000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 77603500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 77603500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33192.216981 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34983.480176 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2508.886918 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2866 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 3770 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.760212 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2507.064055 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 1.822864 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.076510 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.000056 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 2865 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 2873 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2873 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3766 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 253 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5322 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5322 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 128966500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 53203000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 182169500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 182169500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 6631 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 253 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1564 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8195 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8195 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.567938 # miss rate for ReadReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.994885 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.649420 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.649420 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34244.954859 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.159383 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34229.518978 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34229.518978 # average overall miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3766 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 253 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5322 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5322 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 116813500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7843000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48344500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 165158000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 165158000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567938 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994885 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.649420 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.649420 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.923526 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.730077 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
