2005-06-05 07:22:21 +02:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2005 The Regents of The University of Michigan
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2005-06-05 07:22:21 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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2005-06-05 07:22:21 +02:00
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*/
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/** @file
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* Implements a 8250 UART
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*/
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/platform.hh"
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2008-06-18 05:29:06 +02:00
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#include "dev/terminal.hh"
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#include "dev/uart8250.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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2005-06-05 07:22:21 +02:00
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using namespace std;
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Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 08:34:37 +01:00
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using namespace TheISA;
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2005-06-05 07:22:21 +02:00
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Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
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2008-10-09 13:58:24 +02:00
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: uart(u)
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2005-06-05 07:22:21 +02:00
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{
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DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
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intrBit = bit;
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}
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const char *
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2008-02-06 22:32:40 +01:00
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Uart8250::IntrEvent::description() const
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2005-06-05 07:22:21 +02:00
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{
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2007-07-01 02:45:58 +02:00
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return "uart interrupt delay";
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2005-06-05 07:22:21 +02:00
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}
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void
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Uart8250::IntrEvent::process()
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{
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if (intrBit & uart->IER) {
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DPRINTF(Uart, "UART InterEvent, interrupting\n");
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uart->platform->postConsoleInt();
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uart->status |= intrBit;
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2007-04-30 19:13:03 +02:00
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uart->lastTxInt = curTick;
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2005-06-05 07:22:21 +02:00
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}
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else
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DPRINTF(Uart, "UART InterEvent, not interrupting\n");
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}
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/* The linux serial driver (8250.c about line 1182) loops reading from
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* the device until the device reports it has no more data to
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* read. After a maximum of 255 iterations the code prints "serial8250
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* too much work for irq X," and breaks out of the loop. Since the
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* simulated system is so much slower than the actual system, if a
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* user is typing on the keyboard it is very easy for them to provide
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* input at a fast enough rate to not allow the loop to exit and thus
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* the error to be printed. This magic number provides a delay between
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* the time the UART receives a character to send to the simulated
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* system and the time it actually notifies the system it has a
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* character to send to alleviate this problem. --Ali
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*/
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void
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Uart8250::IntrEvent::scheduleIntr()
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{
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static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
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DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
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curTick + interval);
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if (!scheduled())
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2008-10-09 13:58:24 +02:00
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uart->schedule(this, curTick + interval);
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2005-06-05 07:22:21 +02:00
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else
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2008-10-09 13:58:24 +02:00
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uart->reschedule(this, curTick + interval);
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2005-06-05 07:22:21 +02:00
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}
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2007-07-24 06:51:38 +02:00
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Uart8250::Uart8250(const Params *p)
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2007-05-01 18:32:30 +02:00
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: Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
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txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
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2005-06-05 07:22:21 +02:00
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{
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2006-04-06 20:57:51 +02:00
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pioSize = 8;
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2005-06-05 07:22:21 +02:00
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}
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2006-04-06 20:57:51 +02:00
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Tick
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2006-10-20 09:10:12 +02:00
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Uart8250::read(PacketPtr pkt)
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2005-06-05 07:22:21 +02:00
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{
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2006-05-26 20:17:33 +02:00
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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assert(pkt->getSize() == 1);
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2006-04-06 20:57:51 +02:00
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2006-05-26 20:17:33 +02:00
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Addr daddr = pkt->getAddr() - pioAddr;
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2006-05-19 04:32:21 +02:00
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pkt->allocate();
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2006-04-06 20:57:51 +02:00
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2005-06-05 07:22:21 +02:00
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DPRINTF(Uart, " read register %#x\n", daddr);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // read byte
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2008-06-18 05:29:06 +02:00
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if (term->dataAvailable())
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pkt->set(term->in());
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2005-06-05 07:22:21 +02:00
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else {
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2006-05-19 04:32:21 +02:00
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pkt->set((uint8_t)0);
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2005-06-05 07:22:21 +02:00
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// A limited amount of these are ok.
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DPRINTF(Uart, "empty read of RX register\n");
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}
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status &= ~RX_INT;
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platform->clearConsoleInt();
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2008-06-18 05:29:06 +02:00
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if (term->dataAvailable() && (IER & UART_IER_RDI))
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2005-06-05 07:22:21 +02:00
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rxIntrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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2006-05-19 04:32:21 +02:00
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pkt->set(IER);
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2005-06-05 07:22:21 +02:00
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // Intr Identification Register (IIR)
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DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
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2005-08-15 22:59:58 +02:00
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2005-08-16 21:44:57 +02:00
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if (status & RX_INT) /* Rx data interrupt has a higher priority */
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2006-05-19 04:32:21 +02:00
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pkt->set(IIR_RXID);
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2007-04-30 19:13:03 +02:00
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else if (status & TX_INT) {
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2006-05-19 04:32:21 +02:00
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pkt->set(IIR_TXID);
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2007-04-30 19:13:03 +02:00
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//Tx interrupts are cleared on IIR reads
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status &= ~TX_INT;
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} else
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2006-05-19 04:32:21 +02:00
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pkt->set(IIR_NOPEND);
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2005-08-16 21:44:57 +02:00
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2005-06-05 07:22:21 +02:00
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break;
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case 0x3: // Line Control Register (LCR)
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2006-05-19 04:32:21 +02:00
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pkt->set(LCR);
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2005-06-05 07:22:21 +02:00
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break;
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case 0x4: // Modem Control Register (MCR)
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break;
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case 0x5: // Line Status Register (LSR)
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uint8_t lsr;
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lsr = 0;
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// check if there are any bytes to be read
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2008-06-18 05:29:06 +02:00
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if (term->dataAvailable())
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2005-06-05 07:22:21 +02:00
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lsr = UART_LSR_DR;
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lsr |= UART_LSR_TEMT | UART_LSR_THRE;
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2006-05-19 04:32:21 +02:00
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pkt->set(lsr);
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2005-06-05 07:22:21 +02:00
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break;
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case 0x6: // Modem Status Register (MSR)
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2006-05-19 04:32:21 +02:00
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pkt->set((uint8_t)0);
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2005-06-05 07:22:21 +02:00
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break;
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case 0x7: // Scratch Register (SCR)
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2006-05-19 04:32:21 +02:00
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pkt->set((uint8_t)0); // doesn't exist with at 8250.
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2005-06-05 07:22:21 +02:00
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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2006-04-12 23:46:25 +02:00
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/* uint32_t d32 = *data;
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DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
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*/
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2007-06-30 19:16:18 +02:00
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pkt->makeAtomicResponse();
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2006-04-06 20:57:51 +02:00
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return pioDelay;
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2005-06-05 07:22:21 +02:00
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}
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2006-04-06 20:57:51 +02:00
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Tick
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2006-10-20 09:10:12 +02:00
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Uart8250::write(PacketPtr pkt)
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2005-06-05 07:22:21 +02:00
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{
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2006-05-26 20:17:33 +02:00
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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assert(pkt->getSize() == 1);
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2006-04-06 20:57:51 +02:00
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2006-05-26 20:17:33 +02:00
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Addr daddr = pkt->getAddr() - pioAddr;
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2006-04-06 20:57:51 +02:00
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2006-05-19 04:32:21 +02:00
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
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2005-06-05 07:22:21 +02:00
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // write byte
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2008-06-18 05:29:06 +02:00
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term->out(pkt->get<uint8_t>());
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2005-06-05 07:22:21 +02:00
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platform->clearConsoleInt();
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status &= ~TX_INT;
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if (UART_IER_THRI & IER)
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|
|
txIntrEvent.scheduleIntr();
|
|
|
|
} else { // dll divisor latch
|
|
|
|
;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x1:
|
|
|
|
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
2006-05-19 04:32:21 +02:00
|
|
|
IER = pkt->get<uint8_t>();
|
2005-06-05 07:22:21 +02:00
|
|
|
if (UART_IER_THRI & IER)
|
|
|
|
{
|
|
|
|
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
|
2007-04-30 19:13:03 +02:00
|
|
|
if (curTick - lastTxInt >
|
|
|
|
(Tick)((Clock::Float::s / 2e9) * 450)) {
|
|
|
|
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
|
|
|
|
curTick, lastTxInt);
|
|
|
|
txIntrEvent.process();
|
|
|
|
} else {
|
|
|
|
DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
|
|
|
|
curTick, lastTxInt);
|
|
|
|
txIntrEvent.scheduleIntr();
|
|
|
|
}
|
2005-06-05 07:22:21 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
|
|
|
|
if (txIntrEvent.scheduled())
|
2008-10-09 13:58:24 +02:00
|
|
|
deschedule(txIntrEvent);
|
2005-06-05 07:22:21 +02:00
|
|
|
if (status & TX_INT)
|
|
|
|
platform->clearConsoleInt();
|
|
|
|
status &= ~TX_INT;
|
|
|
|
}
|
|
|
|
|
2008-06-18 05:29:06 +02:00
|
|
|
if ((UART_IER_RDI & IER) && term->dataAvailable()) {
|
2005-06-05 07:22:21 +02:00
|
|
|
DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
|
|
|
|
rxIntrEvent.scheduleIntr();
|
|
|
|
} else {
|
|
|
|
DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
|
|
|
|
if (rxIntrEvent.scheduled())
|
2008-10-09 13:58:24 +02:00
|
|
|
deschedule(rxIntrEvent);
|
2005-06-05 07:22:21 +02:00
|
|
|
if (status & RX_INT)
|
|
|
|
platform->clearConsoleInt();
|
|
|
|
status &= ~RX_INT;
|
|
|
|
}
|
|
|
|
} else { // DLM divisor latch MSB
|
|
|
|
;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x2: // FIFO Control Register (FCR)
|
|
|
|
break;
|
|
|
|
case 0x3: // Line Control Register (LCR)
|
2006-05-19 04:32:21 +02:00
|
|
|
LCR = pkt->get<uint8_t>();
|
2005-06-05 07:22:21 +02:00
|
|
|
break;
|
|
|
|
case 0x4: // Modem Control Register (MCR)
|
2006-05-19 04:32:21 +02:00
|
|
|
if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
|
2005-06-05 07:22:21 +02:00
|
|
|
MCR = 0x9A;
|
|
|
|
break;
|
|
|
|
case 0x7: // Scratch Register (SCR)
|
|
|
|
// We are emulating a 8250 so we don't have a scratch reg
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Tried to access a UART port that doesn't exist\n");
|
|
|
|
break;
|
|
|
|
}
|
2007-06-30 19:16:18 +02:00
|
|
|
pkt->makeAtomicResponse();
|
2006-04-06 20:57:51 +02:00
|
|
|
return pioDelay;
|
2005-06-05 07:22:21 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Uart8250::dataAvailable()
|
|
|
|
{
|
|
|
|
// if the kernel wants an interrupt when we have data
|
|
|
|
if (IER & UART_IER_RDI)
|
|
|
|
{
|
|
|
|
platform->postConsoleInt();
|
|
|
|
status |= RX_INT;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2006-04-06 20:57:51 +02:00
|
|
|
void
|
|
|
|
Uart8250::addressRanges(AddrRangeList &range_list)
|
|
|
|
{
|
|
|
|
assert(pioSize != 0);
|
|
|
|
range_list.clear();
|
|
|
|
range_list.push_back(RangeSize(pioAddr, pioSize));
|
|
|
|
}
|
|
|
|
|
2005-06-05 07:22:21 +02:00
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
Uart8250::serialize(ostream &os)
|
|
|
|
{
|
|
|
|
SERIALIZE_SCALAR(status);
|
|
|
|
SERIALIZE_SCALAR(IER);
|
|
|
|
SERIALIZE_SCALAR(DLAB);
|
|
|
|
SERIALIZE_SCALAR(LCR);
|
|
|
|
SERIALIZE_SCALAR(MCR);
|
|
|
|
Tick rxintrwhen;
|
|
|
|
if (rxIntrEvent.scheduled())
|
|
|
|
rxintrwhen = rxIntrEvent.when();
|
|
|
|
else
|
|
|
|
rxintrwhen = 0;
|
|
|
|
Tick txintrwhen;
|
|
|
|
if (txIntrEvent.scheduled())
|
|
|
|
txintrwhen = txIntrEvent.when();
|
|
|
|
else
|
|
|
|
txintrwhen = 0;
|
|
|
|
SERIALIZE_SCALAR(rxintrwhen);
|
|
|
|
SERIALIZE_SCALAR(txintrwhen);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Uart8250::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
{
|
|
|
|
UNSERIALIZE_SCALAR(status);
|
|
|
|
UNSERIALIZE_SCALAR(IER);
|
|
|
|
UNSERIALIZE_SCALAR(DLAB);
|
|
|
|
UNSERIALIZE_SCALAR(LCR);
|
|
|
|
UNSERIALIZE_SCALAR(MCR);
|
|
|
|
Tick rxintrwhen;
|
|
|
|
Tick txintrwhen;
|
|
|
|
UNSERIALIZE_SCALAR(rxintrwhen);
|
|
|
|
UNSERIALIZE_SCALAR(txintrwhen);
|
|
|
|
if (rxintrwhen != 0)
|
2008-10-09 13:58:24 +02:00
|
|
|
schedule(rxIntrEvent, rxintrwhen);
|
2005-06-05 07:22:21 +02:00
|
|
|
if (txintrwhen != 0)
|
2008-10-09 13:58:24 +02:00
|
|
|
schedule(txIntrEvent, txintrwhen);
|
2005-06-05 07:22:21 +02:00
|
|
|
}
|
|
|
|
|
2007-07-24 06:51:38 +02:00
|
|
|
Uart8250 *
|
|
|
|
Uart8250Params::create()
|
2005-06-05 07:22:21 +02:00
|
|
|
{
|
2007-07-24 06:51:38 +02:00
|
|
|
return new Uart8250(this);
|
2005-06-05 07:22:21 +02:00
|
|
|
}
|