2004-05-04 23:01:00 +02:00
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#!/usr/bin/env python
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# Copyright (c) 2004 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# This file generates the header and source files for the flags
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# that control the tracing facility.
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#
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2004-07-03 06:16:38 +02:00
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import sys
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if len(sys.argv) != 2:
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print "%s: Need argument (basename of cc/hh files)" % sys.argv[0]
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sys.exit(1)
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hhfilename = sys.argv[1] + '.hh'
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ccfilename = sys.argv[1] + '.cc'
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2004-05-04 23:01:00 +02:00
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#
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# The list of trace flags that can be used to condition DPRINTFs etc.
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# To define a new flag, simply add it to this list.
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#
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baseFlags = [
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'TCPIP',
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'Bus',
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'ScsiDisk',
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'ScsiCtrl',
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'ScsiNone',
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'DMA',
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'DMAReadVerbose',
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'DMAWriteVerbose',
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'TLB',
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'SimpleDisk',
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'SimpleDiskData',
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'Clock',
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'Regs',
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'MC146818',
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'IPI',
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'Timer',
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'Mbox',
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'PCIA',
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'PCIDEV',
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2004-05-12 04:42:45 +02:00
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'PciConfigAll',
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2004-05-04 23:01:00 +02:00
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'ISP',
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'BADADDR',
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'Console',
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'ConsolePoll',
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'ConsoleVerbose',
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'AlphaConsole',
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'Flow',
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'Interrupt',
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2004-06-15 19:48:08 +02:00
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'Fault',
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2004-05-04 23:01:00 +02:00
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'Cycle',
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'Loader',
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'MMU',
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'Ethernet',
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'EthernetPIO',
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'EthernetDMA',
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'EthernetData',
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l
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
2004-06-21 23:25:18 +02:00
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'EthernetDesc',
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'EthernetIntr',
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'EthernetSM',
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'EthernetCksum',
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2004-05-04 23:01:00 +02:00
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'GDBMisc',
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'GDBAcc',
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'GDBRead',
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'GDBWrite',
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'GDBSend',
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'GDBRecv',
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'GDBExtra',
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'VtoPhys',
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'Printf',
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'DebugPrintf',
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'Serialize',
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'Event',
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'PCEvent',
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'SyscallWarnings',
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'SyscallVerbose',
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'DiskImage',
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'DiskImageRead',
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'DiskImageWrite',
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'InstExec',
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'BPredRAS',
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'Cache',
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'IIC',
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'IICMore',
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'MSHR',
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'Chains',
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2005-02-25 18:41:08 +01:00
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'Pipeline',
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2004-05-04 23:01:00 +02:00
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'Stats',
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2004-05-21 19:57:44 +02:00
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'StatEvents',
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2004-05-04 23:01:00 +02:00
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'Context',
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'Config',
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'Sampler',
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2004-05-12 04:42:45 +02:00
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'WriteBarrier',
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'IdeCtrl',
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'IdeDisk',
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'Tsunami',
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2004-07-11 03:57:59 +02:00
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'Uart',
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2004-07-23 21:52:28 +02:00
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'Split',
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2004-08-19 05:06:51 +02:00
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'SQL',
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2005-01-12 01:00:16 +01:00
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'Thread',
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2004-08-20 20:54:07 +02:00
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'Fetch',
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'Decode',
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'Rename',
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'IEW',
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'Commit',
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'IQ',
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'ROB',
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'FreeList',
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'RenameMap',
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Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
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'LDSTQ',
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'StoreSet',
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'MemDepUnit',
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2004-08-20 20:54:07 +02:00
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'DynInst',
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2005-01-12 00:52:29 +01:00
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'FullCPU',
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2005-02-26 00:00:49 +01:00
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'CommitRate',
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'OoOCPU'
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2004-05-04 23:01:00 +02:00
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]
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#
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# "Compound" flags correspond to a set of base flags. These exist
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# solely for convenience in setting them via the command line: if a
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# compound flag is specified, all of the corresponding base flags are
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# set. Compound flags cannot be used directly in DPRINTFs etc.
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# To define a new compound flag, add a new entry to this hash
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# following the existing examples.
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#
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compoundFlagMap = {
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'GDBAll' : [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv', 'GDBExtra' ],
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'ScsiAll' : [ 'ScsiDisk', 'ScsiCtrl', 'ScsiNone' ],
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'DiskImageAll' : [ 'DiskImage', 'DiskImageRead', 'DiskImageWrite' ],
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l
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
2004-06-21 23:25:18 +02:00
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'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
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2005-01-20 00:18:15 +01:00
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'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
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2004-08-20 20:54:07 +02:00
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'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
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Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
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'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LDSTQ', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU']
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2004-05-04 23:01:00 +02:00
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}
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#############################################################
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#
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# Everything below this point generates the appropriate C++
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# declarations and definitions for the trace flags. If you are simply
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# adding or modifying flag definitions, you should not have to change
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# anything below.
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#
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import sys
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# extract just the compound flag names into a list
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compoundFlags = []
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compoundFlags.extend(compoundFlagMap.keys())
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compoundFlags.sort()
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#
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# First generate the header file. This defines the Flag enum
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|
|
# and some extern declarations for the .cc file.
|
|
|
|
#
|
|
|
|
try:
|
|
|
|
hhfile = file(hhfilename, 'w')
|
|
|
|
except IOError, e:
|
|
|
|
sys.exit("can't open %s: %s" % (hhfilename, e))
|
|
|
|
|
|
|
|
# file header boilerplate
|
|
|
|
print >>hhfile, '''/* $Id $ */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Copyright (c) 2004
|
|
|
|
* The Regents of The University of Michigan
|
|
|
|
* All Rights Reserved
|
|
|
|
*
|
|
|
|
* This code is part of the M5 simulator, developed by Nathan Binkert,
|
|
|
|
* Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
|
|
|
|
* from Ron Dreslinski, Dave Greene, and Lisa Hsu.
|
|
|
|
*
|
|
|
|
* Permission is granted to use, copy, create derivative works and
|
|
|
|
* redistribute this software and such derivative works for any
|
|
|
|
* purpose, so long as the copyright notice above, this grant of
|
|
|
|
* permission, and the disclaimer below appear in all copies made; and
|
|
|
|
* so long as the name of The University of Michigan is not used in
|
|
|
|
* any advertising or publicity pertaining to the use or distribution
|
|
|
|
* of this software without specific, written prior authorization.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
|
|
|
|
* UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
|
|
|
|
* WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
|
|
|
|
* EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
|
|
|
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
|
|
* PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
|
|
|
|
* LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
|
|
|
|
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
|
|
|
|
* ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
|
|
|
|
* IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
|
|
|
|
* DAMAGES.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DO NOT EDIT THIS FILE!
|
|
|
|
*
|
|
|
|
* Automatically generated from traceflags.py
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __BASE_TRACE_FLAGS_HH__
|
|
|
|
#define __BASE_TRACE_FLAGS_HH__
|
|
|
|
|
|
|
|
namespace Trace {
|
|
|
|
|
|
|
|
enum Flags {
|
|
|
|
''',
|
|
|
|
|
|
|
|
# Generate the enum. Base flags come first, then compound flags.
|
|
|
|
idx = 0
|
|
|
|
for flag in baseFlags:
|
|
|
|
print >>hhfile, ' %s = %d,' % (flag, idx)
|
|
|
|
idx += 1
|
|
|
|
|
|
|
|
numBaseFlags = idx
|
|
|
|
print >>hhfile, ' NumFlags = %d,' % idx
|
|
|
|
|
|
|
|
# put a comment in here to separate base from compound flags
|
|
|
|
print >>hhfile, '''
|
|
|
|
// The remaining enum values are *not* valid indices for Trace::flags.
|
|
|
|
// They are "compound" flags, which correspond to sets of base
|
|
|
|
// flags, and are used only by TraceParamContext::setFlags().
|
|
|
|
''',
|
|
|
|
|
|
|
|
for flag in compoundFlags:
|
|
|
|
print >>hhfile, ' %s = %d,' % (flag, idx)
|
|
|
|
idx += 1
|
|
|
|
|
|
|
|
numCompoundFlags = idx - numBaseFlags
|
|
|
|
print >>hhfile, ' NumCompoundFlags = %d' % numCompoundFlags
|
|
|
|
|
|
|
|
# trailer boilerplate
|
|
|
|
print >>hhfile, '''\
|
|
|
|
}; // enum Flags
|
|
|
|
|
|
|
|
// Array of strings for SimpleEnumParam
|
|
|
|
extern const char *flagStrings[];
|
|
|
|
extern const int numFlagStrings;
|
|
|
|
|
|
|
|
// Array of arraay pointers: for each compound flag, gives the list of
|
|
|
|
// base flags to set. Inidividual flag arrays are terminated by -1.
|
|
|
|
extern const Flags *compoundFlags[];
|
|
|
|
|
|
|
|
/* namespace Trace */ }
|
|
|
|
|
|
|
|
#endif // __BASE_TRACE_FLAGS_HH__
|
|
|
|
''',
|
|
|
|
|
|
|
|
hhfile.close()
|
|
|
|
|
|
|
|
#
|
|
|
|
#
|
|
|
|
# Print out .cc file with array definitions.
|
|
|
|
#
|
|
|
|
#
|
|
|
|
try:
|
|
|
|
ccfile = file(ccfilename, 'w')
|
|
|
|
except OSError, e:
|
|
|
|
sys.exit("can't open %s: %s" % (ccfilename, e))
|
|
|
|
|
|
|
|
# file header
|
|
|
|
print >>ccfile, '''\
|
|
|
|
/* $Id $ */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Copyright (c) 2004
|
|
|
|
* The Regents of The University of Michigan
|
|
|
|
* All Rights Reserved
|
|
|
|
*
|
|
|
|
* This code is part of the M5 simulator, developed by Nathan Binkert,
|
|
|
|
* Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
|
|
|
|
* from Ron Dreslinski, Dave Greene, and Lisa Hsu.
|
|
|
|
*
|
|
|
|
* Permission is granted to use, copy, create derivative works and
|
|
|
|
* redistribute this software and such derivative works for any
|
|
|
|
* purpose, so long as the copyright notice above, this grant of
|
|
|
|
* permission, and the disclaimer below appear in all copies made; and
|
|
|
|
* so long as the name of The University of Michigan is not used in
|
|
|
|
* any advertising or publicity pertaining to the use or distribution
|
|
|
|
* of this software without specific, written prior authorization.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
|
|
|
|
* UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
|
|
|
|
* WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
|
|
|
|
* EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
|
|
|
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
|
|
* PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
|
|
|
|
* LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
|
|
|
|
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
|
|
|
|
* ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
|
|
|
|
* IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
|
|
|
|
* DAMAGES.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DO NOT EDIT THIS FILE!
|
|
|
|
*
|
|
|
|
* Automatically generated from traceflags.pl.
|
|
|
|
*/
|
|
|
|
|
2004-05-06 18:09:54 +02:00
|
|
|
#include "base/traceflags.hh"
|
2004-05-04 23:01:00 +02:00
|
|
|
|
|
|
|
using namespace Trace;
|
|
|
|
|
|
|
|
const char *Trace::flagStrings[] =
|
|
|
|
{
|
|
|
|
''',
|
|
|
|
|
|
|
|
# The string array is used by SimpleEnumParam to map the strings
|
|
|
|
# provided by the user to enum values.
|
|
|
|
for flag in baseFlags:
|
|
|
|
print >>ccfile, ' "%s",' % flag
|
|
|
|
|
|
|
|
for flag in compoundFlags:
|
|
|
|
print >>ccfile, ' "%s",' % flag
|
|
|
|
|
|
|
|
print >>ccfile, '};\n'
|
|
|
|
|
|
|
|
numFlagStrings = len(baseFlags) + len(compoundFlags);
|
|
|
|
|
|
|
|
print >>ccfile, 'const int Trace::numFlagStrings = %d;' % numFlagStrings
|
|
|
|
print >>ccfile
|
|
|
|
|
|
|
|
#
|
|
|
|
# Now define the individual compound flag arrays. There is an array
|
|
|
|
# for each compound flag listing the component base flags.
|
|
|
|
#
|
|
|
|
|
|
|
|
for flag in compoundFlags:
|
|
|
|
flags = compoundFlagMap[flag]
|
|
|
|
flags.append('(Flags)-1')
|
|
|
|
print >>ccfile, 'static const Flags %sMap[] =' % flag
|
|
|
|
print >>ccfile, '{ %s };' % (', '.join(flags))
|
|
|
|
print >>ccfile
|
|
|
|
|
|
|
|
#
|
|
|
|
# Finally the compoundFlags[] array maps the compound flags
|
|
|
|
# to their individual arrays/
|
|
|
|
#
|
|
|
|
print >>ccfile, 'const Flags *Trace::compoundFlags[] ='
|
|
|
|
print >>ccfile, '{'
|
|
|
|
|
|
|
|
for flag in compoundFlags:
|
|
|
|
print >>ccfile, ' %sMap,' % flag
|
|
|
|
|
|
|
|
# file trailer
|
|
|
|
print >>ccfile, '};'
|
|
|
|
|
|
|
|
ccfile.close()
|
|
|
|
|