2013-03-07 04:57:10 +01:00
|
|
|
Real time: Mar/06/2013 20:31:07
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
Profiler Stats
|
|
|
|
--------------
|
2012-07-11 07:51:55 +02:00
|
|
|
Elapsed_time_in_seconds: 0
|
|
|
|
Elapsed_time_in_minutes: 0
|
|
|
|
Elapsed_time_in_hours: 0
|
|
|
|
Elapsed_time_in_days: 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2013-03-07 04:57:10 +01:00
|
|
|
Virtual_time_in_seconds: 0.51
|
|
|
|
Virtual_time_in_minutes: 0.0085
|
|
|
|
Virtual_time_in_hours: 0.000141667
|
|
|
|
Virtual_time_in_days: 5.90278e-06
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2012-09-10 19:44:03 +02:00
|
|
|
Ruby_current_time: 52498
|
2010-01-30 05:29:40 +01:00
|
|
|
Ruby_start_time: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
Ruby_cycles: 52498
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2013-03-07 04:57:10 +01:00
|
|
|
mbytes_resident: 53.0938
|
|
|
|
mbytes_total: 145.422
|
|
|
|
resident_ratio: 0.365182
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2012-09-10 19:44:03 +02:00
|
|
|
ruby_cycles_executed: [ 52499 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
Busy Controller Counts:
|
|
|
|
L1Cache-0:0
|
|
|
|
Directory-0:0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
Busy Bank Count:0
|
|
|
|
|
2010-01-30 05:29:40 +01:00
|
|
|
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
All Non-Zero Cycle Demand Cache Accesses
|
|
|
|
----------------------------------------
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency: [binsize: 1 max: 94 count: 3294 average: 14.9375 | standard deviation: 24.8042 | 0 0 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 4 7 128 221 203 1 2 1 2 7 11 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 4 18 11 0 1 ]
|
|
|
|
miss_latency_LD: [binsize: 1 max: 92 count: 415 average: 40.3325 | standard deviation: 31.5967 | 0 0 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 44 94 74 0 2 0 1 2 5 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 9 6 ]
|
|
|
|
miss_latency_ST: [binsize: 1 max: 92 count: 294 average: 20.9456 | standard deviation: 28.6341 | 0 0 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 16 31 29 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ]
|
|
|
|
miss_latency_IFETCH: [binsize: 1 max: 94 count: 2585 average: 10.1772 | standard deviation: 20.0197 | 0 0 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 68 96 100 1 0 0 1 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 6 4 0 1 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ]
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency_Directory: [binsize: 1 max: 94 count: 626 average: 65.8147 | standard deviation: 6.37759 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 4 7 128 221 203 1 2 1 2 7 11 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 4 18 11 0 1 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
imcomplete_wCC_Times: 0
|
|
|
|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
|
|
|
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
|
|
|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
imcomplete_dir_Times: 625
|
|
|
|
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ]
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency_LD_Directory: [binsize: 1 max: 92 count: 245 average: 66.2367 | standard deviation: 7.0079 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 44 94 74 0 2 0 1 2 5 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 9 6 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ]
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency_ST_Directory: [binsize: 1 max: 92 count: 84 average: 65.8095 | standard deviation: 6.52244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 16 31 29 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ]
|
2011-04-20 03:45:23 +02:00
|
|
|
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ]
|
2012-09-10 19:44:03 +02:00
|
|
|
miss_latency_IFETCH_Directory: [binsize: 1 max: 94 count: 297 average: 65.468 | standard deviation: 5.76218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 68 96 100 1 0 0 1 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 6 4 0 1 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
|
|
------------------------------------
|
|
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Request vs. RubySystem State Profile
|
|
|
|
--------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
|
|
|
Message Delayed Cycles
|
|
|
|
----------------------
|
2010-01-30 05:29:40 +01:00
|
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
|
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average: 0 | standard deviation: 0 | 626 ]
|
|
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average: 0 | standard deviation: 0 | 622 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-07-07 00:49:48 +02:00
|
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
|
|
|
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
Resource Usage
|
|
|
|
--------------
|
|
|
|
page_size: 4096
|
|
|
|
user_time: 0
|
|
|
|
system_time: 0
|
2013-03-07 04:57:10 +01:00
|
|
|
page_reclaims: 10892
|
2013-02-11 04:43:23 +01:00
|
|
|
page_faults: 0
|
2009-05-11 19:38:46 +02:00
|
|
|
swaps: 0
|
2013-03-07 04:57:10 +01:00
|
|
|
block_inputs: 1328
|
2013-02-11 04:43:23 +01:00
|
|
|
block_outputs: 88
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
Network Stats
|
|
|
|
-------------
|
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
total_msg_count_Control: 1878 15024
|
|
|
|
total_msg_count_Data: 1866 134352
|
|
|
|
total_msg_count_Response_Data: 1878 135216
|
|
|
|
total_msg_count_Writeback_Control: 1866 14928
|
|
|
|
total_msgs: 7488 total_bytes: 299520
|
|
|
|
|
2009-07-07 00:49:48 +02:00
|
|
|
switch_0_inlinks: 2
|
|
|
|
switch_0_outlinks: 2
|
2012-09-10 19:44:03 +02:00
|
|
|
links_utilized_percent_switch_0: 5.94308
|
|
|
|
links_utilized_percent_switch_0_link_0: 5.95832 bw: 16000 base_latency: 1
|
|
|
|
links_utilized_percent_switch_0_link_1: 5.92784 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2009-07-07 00:49:48 +02:00
|
|
|
switch_1_inlinks: 2
|
|
|
|
switch_1_outlinks: 2
|
2012-09-10 19:44:03 +02:00
|
|
|
links_utilized_percent_switch_1: 5.94308
|
|
|
|
links_utilized_percent_switch_1_link_0: 5.92784 bw: 16000 base_latency: 1
|
|
|
|
links_utilized_percent_switch_1_link_1: 5.95832 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
switch_2_inlinks: 2
|
|
|
|
switch_2_outlinks: 2
|
2012-09-10 19:44:03 +02:00
|
|
|
links_utilized_percent_switch_2: 5.94308
|
|
|
|
links_utilized_percent_switch_2_link_0: 5.95832 bw: 16000 base_latency: 1
|
|
|
|
links_utilized_percent_switch_2_link_1: 5.92784 bw: 16000 base_latency: 1
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
Cache Stats: system.ruby.l1_cntrl0.cacheMemory
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_misses: 626
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_demand_misses: 626
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
system.ruby.l1_cntrl0.cacheMemory_request_type_LD: 39.1374%
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_request_type_ST: 13.4185%
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_request_type_IFETCH: 47.4441%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
system.ruby.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 626 100%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- L1Cache ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-08 04:23:13 +01:00
|
|
|
Load [415 ] 415
|
|
|
|
Ifetch [2585 ] 2585
|
|
|
|
Store [294 ] 294
|
|
|
|
Data [626 ] 626
|
|
|
|
Fwd_GETX [0 ] 0
|
|
|
|
Inv [0 ] 0
|
|
|
|
Replacement [622 ] 622
|
|
|
|
Writeback_Ack [622 ] 622
|
|
|
|
Writeback_Nack [0 ] 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I Load [245 ] 245
|
|
|
|
I Ifetch [297 ] 297
|
|
|
|
I Store [84 ] 84
|
|
|
|
I Inv [0 ] 0
|
|
|
|
I Replacement [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
II Writeback_Nack [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
M Load [170 ] 170
|
|
|
|
M Ifetch [2288 ] 2288
|
|
|
|
M Store [210 ] 210
|
|
|
|
M Fwd_GETX [0 ] 0
|
|
|
|
M Inv [0 ] 0
|
|
|
|
M Replacement [622 ] 622
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MI Fwd_GETX [0 ] 0
|
|
|
|
MI Inv [0 ] 0
|
|
|
|
MI Writeback_Ack [622 ] 622
|
|
|
|
MI Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MII Fwd_GETX [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IS Data [542 ] 542
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IM Data [84 ] 84
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_total_requests: 1248
|
|
|
|
memory_reads: 626
|
|
|
|
memory_writes: 622
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_refreshes: 365
|
|
|
|
memory_total_request_delays: 915
|
|
|
|
memory_delays_per_request: 0.733173
|
|
|
|
memory_delays_in_input_queue: 0
|
|
|
|
memory_delays_behind_head_of_bank_queue: 0
|
|
|
|
memory_delays_stalled_at_head_of_bank_queue: 915
|
|
|
|
memory_stalls_for_bank_busy: 352
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_random_busy: 0
|
|
|
|
memory_stalls_for_anti_starvation: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_stalls_for_arbitration: 40
|
|
|
|
memory_stalls_for_bus: 497
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_tfaw: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_stalls_for_read_write_turnaround: 26
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_read_read_turnaround: 0
|
|
|
|
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- Directory ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-08 04:23:13 +01:00
|
|
|
GETX [626 ] 626
|
|
|
|
GETS [0 ] 0
|
|
|
|
PUTX [622 ] 622
|
|
|
|
PUTX_NotOwner [0 ] 0
|
|
|
|
DMA_READ [0 ] 0
|
|
|
|
DMA_WRITE [0 ] 0
|
|
|
|
Memory_Data [626 ] 626
|
|
|
|
Memory_Ack [622 ] 622
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I GETX [626 ] 626
|
|
|
|
I PUTX_NotOwner [0 ] 0
|
|
|
|
I DMA_READ [0 ] 0
|
|
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
M GETX [0 ] 0
|
|
|
|
M PUTX [622 ] 622
|
|
|
|
M PUTX_NotOwner [0 ] 0
|
|
|
|
M DMA_READ [0 ] 0
|
|
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
M_DRD GETX [0 ] 0
|
|
|
|
M_DRD PUTX [0 ] 0
|
|
|
|
|
|
|
|
M_DWR GETX [0 ] 0
|
|
|
|
M_DWR PUTX [0 ] 0
|
|
|
|
|
|
|
|
M_DWRI GETX [0 ] 0
|
|
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
M_DRDI GETX [0 ] 0
|
|
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
IM GETX [0 ] 0
|
|
|
|
IM GETS [0 ] 0
|
|
|
|
IM PUTX [0 ] 0
|
|
|
|
IM PUTX_NotOwner [0 ] 0
|
|
|
|
IM DMA_READ [0 ] 0
|
|
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
IM Memory_Data [626 ] 626
|
|
|
|
|
|
|
|
MI GETX [0 ] 0
|
|
|
|
MI GETS [0 ] 0
|
|
|
|
MI PUTX [0 ] 0
|
|
|
|
MI PUTX_NotOwner [0 ] 0
|
|
|
|
MI DMA_READ [0 ] 0
|
|
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
MI Memory_Ack [622 ] 622
|
|
|
|
|
|
|
|
ID GETX [0 ] 0
|
|
|
|
ID GETS [0 ] 0
|
|
|
|
ID PUTX [0 ] 0
|
|
|
|
ID PUTX_NotOwner [0 ] 0
|
|
|
|
ID DMA_READ [0 ] 0
|
|
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
ID Memory_Data [0 ] 0
|
|
|
|
|
|
|
|
ID_W GETX [0 ] 0
|
|
|
|
ID_W GETS [0 ] 0
|
|
|
|
ID_W PUTX [0 ] 0
|
|
|
|
ID_W PUTX_NotOwner [0 ] 0
|
|
|
|
ID_W DMA_READ [0 ] 0
|
|
|
|
ID_W DMA_WRITE [0 ] 0
|
2012-01-25 18:19:50 +01:00
|
|
|
ID_W Memory_Ack [0 ] 0
|
|
|
|
|