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gem5/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt

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inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
---------- Begin Simulation Statistics ----------
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
sim_seconds 0.041834 # Number of seconds simulated
sim_ticks 41833966000 # Number of ticks simulated
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
host_inst_rate 47398 # Simulator instruction rate (inst/s)
host_tick_rate 21575287 # Simulator tick rate (ticks/s)
host_mem_usage 249684 # Number of bytes of host memory used
host_seconds 1938.98 # Real time elapsed on the host
inorder: regr-update: reduce dynamic mem. use to speedup sims previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 20:31:37 +01:00
sim_insts 91903056 # Number of instructions simulated
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996214 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996224 # DTB read accesses
system.cpu.dtb.write_hits 6501905 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501928 # DTB write accesses
system.cpu.dtb.data_hits 26498119 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498152 # DTB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_hits 9991202 # ITB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_accesses 9991251 # ITB accesses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numCycles 83667933 # number of cpu cycles simulated
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed.
system.cpu.activity 90.796172 # Percentage of cycles cpu is active
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
2010-11-08 20:58:24 +01:00
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
inorder: regr-update: reduce dynamic mem. use to speedup sims previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 20:31:37 +01:00
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
inorder: regr-update: reduce dynamic mem. use to speedup sims previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 20:31:37 +01:00
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads
system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26652325 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7551 # number of replacements
system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use
system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits
system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits
system.cpu.icache.overall_hits 9979713 # number of overall hits
system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses
system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11486 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 26491206 # number of overall hits
system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 6095 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.cache_copies 0 # number of cache copies performed
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.writebacks 107 # number of writebacks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks.
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6721 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses)
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.writebacks 0 # number of writebacks
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
inorder: update SE regressions
2011-06-20 03:43:42 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
inorder-regress: add twolf ALPHA-SE
2009-05-12 21:01:16 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink