2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.747000 # Number of seconds simulated
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sim_ticks 746999805000 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 52755 # Simulator instruction rate (inst/s)
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host_tick_rate 24303440 # Simulator tick rate (ticks/s)
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host_mem_usage 253604 # Number of bytes of host memory used
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host_seconds 30736.38 # Real time elapsed on the host
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2011-02-05 09:16:09 +01:00
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sim_insts 1621493982 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 48 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 1493999611 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 183981284 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 183981284 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 7273832 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 175979129 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 174823422 # Number of BTB hits
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.icacheStallCycles 199101325 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1418187336 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 183981284 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 174823422 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 411931747 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 120581871 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 775842898 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 439 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 187933146 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1412014 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1493732032 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.734289 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.070436 # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::0 1084944891 72.63% 72.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 27695152 1.85% 74.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 18612240 1.25% 75.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 16931022 1.13% 76.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 30747713 2.06% 78.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 17254642 1.16% 80.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 38005540 2.54% 82.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 38774045 2.60% 85.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 220766787 14.78% 100.00% # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::total 1493732032 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.123147 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.949255 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 299784199 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 683008972 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 314849688 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 89233622 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 106855551 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 2563435147 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 106855551 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 360599256 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 188215169 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 3353 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 328972953 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 509085750 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2506842740 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 353300714 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 135977984 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 2507364398 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 6062894034 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 6062889786 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 4248 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.UndoneMaps 889369748 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 162 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 162 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 860776772 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 644217579 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 260359160 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 564219162 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 219825369 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2437807916 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 95 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1879814445 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 473311 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 816283522 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1731057121 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1493732032 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.258468 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.208875 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 432191127 28.93% 28.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 591005322 39.57% 68.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 246823296 16.52% 85.02% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 135579868 9.08% 94.10% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 59328852 3.97% 98.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 22913004 1.53% 99.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 4862881 0.33% 99.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 856243 0.06% 99.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 171439 0.01% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::total 1493732032 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 145103 3.04% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 3853337 80.69% 83.73% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 777052 16.27% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 26397138 1.40% 1.40% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1212079345 64.48% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.88% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 449002654 23.89% 89.77% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 192335308 10.23% 100.00% # Type of FU issued
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::total 1879814445 # Type of FU issued
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system.cpu.iq.rate 1.258243 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 4775492 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.002540 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 5258609690 # Number of integer instruction queue reads
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|
|
system.cpu.iq.int_inst_queue_writes 3260533161 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1853774167 # Number of integer instruction queue wakeup accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_writes 1274 # Number of floating instruction queue writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 1858192780 # Number of integer alu accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 120571651 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 225175454 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6636 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 6448917 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 72173103 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 67 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 30868 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 106855551 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 4276997 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 154006 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2437808011 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 3809571 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 644217579 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 260359160 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 92996 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 6448917 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4522013 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 2931532 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 7453545 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1858657499 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 444749829 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 21156946 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_refs 636612361 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 111987428 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 191862532 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.244082 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1856615108 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1853774179 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1441885120 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2107634936 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.240813 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.684125 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 816323432 # The number of squashed insts skipped by commit
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 7273892 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 1386876481 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.169170 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.394530 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 510181205 36.79% 36.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 529583219 38.19% 74.97% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 122943422 8.86% 83.84% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 138376651 9.98% 93.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 42654329 3.08% 96.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 24144434 1.74% 98.63% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 5177613 0.37% 99.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 2036062 0.15% 99.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 11779546 0.85% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 1386876481 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.count 1621493982 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 607228182 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 419042125 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 107161579 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 11779546 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 3812914349 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4982493999 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 44138 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 267579 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.cpi 0.921372 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.921372 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.085338 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.085338 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3240601354 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1846777221 # number of integer regfile writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 936479302 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 14 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 820.004984 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 187931883 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 908 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 206973.439427 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 820.004984 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.400393 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 187931883 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 187931883 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 187931883 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1263 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1263 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1263 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 44191500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 44191500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 44191500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 187933146 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 187933146 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 187933146 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34989.311164 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34989.311164 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34989.311164 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 355 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 355 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 355 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 32070500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 32070500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 32070500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.replacements 459464 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4095.142322 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 510865684 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 463560 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 1102.048675 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 317747000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4095.142322 # Average occupied blocks per context
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 323944700 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 186920984 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 510865684 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 510865684 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 217118 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1265073 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 1482191 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1482191 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 2201155000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 24662905498 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 26864060498 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 26864060498 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 324161818 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 512347875 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 512347875 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000670 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.006722 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.002893 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.002893 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 18124.560531 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 18124.560531 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 1608500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 471924500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 447 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 29514 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3598.434004 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 410359 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 3236 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1015395 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1018631 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1018631 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 213882 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 249678 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 463560 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 463560 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1535369000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2499634500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4035003500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4035003500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.579778 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.replacements 73641 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 18052.437933 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 453217 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 89251 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 5.078005 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1921.052649 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 16131.385284 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.058626 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.492291 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 181658 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 410359 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 190902 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 372560 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 372560 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 33126 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 58782 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 91908 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 91908 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1130437500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2022399000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 3152836500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 3152836500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 214784 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 410359 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 249684 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 464468 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 464468 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.154229 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235426 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.197878 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.197878 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34304.266223 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34304.266223 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1076.388889 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 58527 # number of writebacks
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 33126 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 58782 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 91908 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 91908 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1027129500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1831638000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2858767500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2858767500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154229 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235426 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.197878 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.197878 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
