2005-02-26 00:00:49 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2005 The Regents of The University of Michigan
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2005-02-26 00:00:49 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2006-04-23 00:45:01 +02:00
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#ifndef __CPU_OZONE_CPU_HH__
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#define __CPU_OZONE_CPU_HH__
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#include <set>
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2005-02-26 00:00:49 +01:00
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#include "base/statistics.hh"
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2006-04-23 00:45:01 +02:00
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#include "base/timebuf.hh"
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2005-08-30 19:18:54 +02:00
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#include "config/full_system.hh"
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2005-06-05 02:50:10 +02:00
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#include "cpu/base.hh"
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2005-02-26 00:00:49 +01:00
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#include "cpu/exec_context.hh"
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2006-04-23 00:45:01 +02:00
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/ozone/thread_state.hh"
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2005-02-26 00:00:49 +01:00
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "mem/mem_interface.hh"
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#include "sim/eventq.hh"
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// forward declarations
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2005-08-30 19:18:54 +02:00
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#if FULL_SYSTEM
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2006-04-23 00:45:01 +02:00
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#include "arch/alpha/tlb.hh"
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2005-02-26 00:00:49 +01:00
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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2006-04-23 00:45:01 +02:00
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class MemoryController;
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2005-02-26 00:00:49 +01:00
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
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class Sampler;
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2005-02-26 00:00:49 +01:00
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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class Checkpoint;
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2006-05-16 20:09:04 +02:00
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class EndQuiesceEvent;
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2005-02-26 00:00:49 +01:00
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class MemInterface;
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namespace Trace {
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class InstRecord;
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}
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
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template <class>
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class Checker;
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2005-02-26 00:00:49 +01:00
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/**
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* Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
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* simple out-of-order capabilities added to it. It is still a 1 CPI machine
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* (?), but is capable of handling cache misses. Basically it models having
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* a ROB/IQ by only allowing a certain amount of instructions to execute while
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* the cache miss is outstanding.
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*/
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template <class Impl>
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2006-04-23 00:45:01 +02:00
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class OzoneCPU : public BaseCPU
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2005-02-26 00:00:49 +01:00
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{
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private:
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2006-04-23 00:45:01 +02:00
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typedef typename Impl::FrontEnd FrontEnd;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::DynInst DynInst;
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2005-02-26 00:00:49 +01:00
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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2006-04-23 00:45:01 +02:00
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typedef TheISA::MiscReg MiscReg;
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public:
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class OzoneXC : public ExecContext {
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public:
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OzoneCPU<Impl> *cpu;
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OzoneThreadState<Impl> *thread;
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BaseCPU *getCpuPtr();
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void setCpuId(int id);
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int readCpuId() { return thread->cpuId; }
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FunctionalMemory *getMemPtr() { return thread->mem; }
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#if FULL_SYSTEM
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System *getSystemPtr() { return cpu->system; }
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PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
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AlphaITB *getITBPtr() { return cpu->itb; }
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AlphaDTB * getDTBPtr() { return cpu->dtb; }
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#else
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Process *getProcessPtr() { return thread->process; }
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#endif
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Status status() const { return thread->_status; }
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void setStatus(Status new_status);
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Unallocated.
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void deallocate();
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/// Set the status to Halted.
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void halt();
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#if FULL_SYSTEM
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void dumpFuncProfile();
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#endif
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void takeOverFrom(ExecContext *old_context);
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void regStats(const std::string &name);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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2006-05-16 20:09:04 +02:00
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EndQuiesceEvent *getQuiesceEvent();
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2006-04-23 00:45:01 +02:00
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Tick readLastActivate();
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Tick readLastSuspend();
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void profileClear();
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void profileSample();
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#endif
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int getThreadNum();
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// Also somewhat obnoxious. Really only used for the TLB fault.
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TheISA::MachInst getInst();
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void copyArchRegs(ExecContext *xc);
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void clearArchRegs();
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uint64_t readIntReg(int reg_idx);
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float readFloatRegSingle(int reg_idx);
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double readFloatRegDouble(int reg_idx);
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uint64_t readFloatRegInt(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatRegSingle(int reg_idx, float val);
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void setFloatRegDouble(int reg_idx, double val);
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void setFloatRegInt(int reg_idx, uint64_t val);
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uint64_t readPC() { return thread->PC; }
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void setPC(Addr val);
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uint64_t readNextPC() { return thread->nextPC; }
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void setNextPC(Addr val);
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public:
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// ISA stuff:
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MiscReg readMiscReg(int misc_reg);
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
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Fault setMiscReg(int misc_reg, const MiscReg &val);
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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bool inPalMode() { return cpu->inPalMode(); }
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#endif
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bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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{ return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
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// used to shift args for indirect syscall
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void setSyscallArg(int i, TheISA::IntReg val)
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{ thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
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void setSyscallReturn(SyscallReturn return_value)
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{ cpu->setSyscallReturn(return_value, thread->tid); }
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Counter readFuncExeInst() { return thread->funcExeInst; }
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void setFuncExeInst(Counter new_val)
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{ thread->funcExeInst = new_val; }
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#endif
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};
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// execution context proxy
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
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OzoneXC ozoneXC;
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ExecContext *xcProxy;
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ExecContext *checkerXC;
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2006-04-23 00:45:01 +02:00
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typedef OzoneThreadState<Impl> ImplState;
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private:
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OzoneThreadState<Impl> thread;
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/*
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// Squash event for when the XC needs to squash all inflight instructions.
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struct XCSquashEvent : public Event
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{
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void process();
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const char *description();
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};
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*/
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2005-02-26 00:00:49 +01:00
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public:
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// main simulation loop (one cycle)
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void tick();
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2006-04-23 00:45:01 +02:00
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std::set<InstSeqNum> snList;
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
std::set<Addr> lockAddrList;
|
2005-02-26 00:00:49 +01:00
|
|
|
private:
|
|
|
|
struct TickEvent : public Event
|
|
|
|
{
|
2006-04-23 00:45:01 +02:00
|
|
|
OzoneCPU *cpu;
|
2005-02-26 00:00:49 +01:00
|
|
|
int width;
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
TickEvent(OzoneCPU *c, int w);
|
2005-02-26 00:00:49 +01:00
|
|
|
void process();
|
|
|
|
const char *description();
|
|
|
|
};
|
|
|
|
|
|
|
|
TickEvent tickEvent;
|
|
|
|
|
|
|
|
/// Schedule tick event, regardless of its current state.
|
|
|
|
void scheduleTickEvent(int delay)
|
|
|
|
{
|
|
|
|
if (tickEvent.squashed())
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
tickEvent.reschedule(curTick + cycles(delay));
|
2005-02-26 00:00:49 +01:00
|
|
|
else if (!tickEvent.scheduled())
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
tickEvent.schedule(curTick + cycles(delay));
|
2005-02-26 00:00:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Unschedule tick event, regardless of its current state.
|
|
|
|
void unscheduleTickEvent()
|
|
|
|
{
|
|
|
|
if (tickEvent.scheduled())
|
|
|
|
tickEvent.squash();
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
Trace::InstRecord *traceData;
|
|
|
|
|
|
|
|
template<typename T>
|
|
|
|
void trace_data(T data);
|
|
|
|
|
|
|
|
public:
|
|
|
|
//
|
|
|
|
enum Status {
|
|
|
|
Running,
|
|
|
|
Idle,
|
|
|
|
SwitchedOut
|
|
|
|
};
|
|
|
|
|
|
|
|
Status _status;
|
|
|
|
|
|
|
|
public:
|
2006-04-23 00:45:01 +02:00
|
|
|
bool checkInterrupts;
|
|
|
|
|
2005-02-26 00:00:49 +01:00
|
|
|
void post_interrupt(int int_num, int index);
|
|
|
|
|
|
|
|
void zero_fill_64(Addr addr) {
|
|
|
|
static int warned = 0;
|
|
|
|
if (!warned) {
|
|
|
|
warn ("WH64 is not implemented");
|
|
|
|
warned = 1;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
typedef typename Impl::Params Params;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
OzoneCPU(Params *params);
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
virtual ~OzoneCPU();
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2005-05-03 16:56:47 +02:00
|
|
|
void init();
|
|
|
|
|
2005-02-26 00:00:49 +01:00
|
|
|
public:
|
2006-04-23 00:45:01 +02:00
|
|
|
BaseCPU *getCpuPtr() { return this; }
|
|
|
|
|
|
|
|
void setCpuId(int id) { cpuId = id; }
|
|
|
|
|
|
|
|
int readCpuId() { return cpuId; }
|
|
|
|
|
|
|
|
// FunctionalMemory *getMemPtr() { return mem; }
|
|
|
|
|
|
|
|
int cpuId;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
void switchOut(Sampler *sampler);
|
2006-05-16 20:09:04 +02:00
|
|
|
void signalSwitched();
|
2005-02-26 00:00:49 +01:00
|
|
|
void takeOverFrom(BaseCPU *oldCPU);
|
|
|
|
|
2006-05-16 20:09:04 +02:00
|
|
|
Sampler *sampler;
|
|
|
|
|
|
|
|
int switchCount;
|
|
|
|
|
2005-08-30 19:18:54 +02:00
|
|
|
#if FULL_SYSTEM
|
2005-02-26 00:00:49 +01:00
|
|
|
Addr dbg_vtophys(Addr addr);
|
|
|
|
|
|
|
|
bool interval_stats;
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
AlphaITB *itb;
|
|
|
|
AlphaDTB *dtb;
|
|
|
|
System *system;
|
|
|
|
|
|
|
|
// the following two fields are redundant, since we can always
|
|
|
|
// look them up through the system pointer, but we'll leave them
|
|
|
|
// here for now for convenience
|
|
|
|
MemoryController *memctrl;
|
|
|
|
PhysicalMemory *physmem;
|
2005-02-26 00:00:49 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
// L1 instruction cache
|
|
|
|
MemInterface *icacheInterface;
|
|
|
|
|
|
|
|
// L1 data cache
|
|
|
|
MemInterface *dcacheInterface;
|
|
|
|
|
2006-04-24 23:10:06 +02:00
|
|
|
/** Pointer to memory. */
|
|
|
|
FunctionalMemory *mem;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
FrontEnd *frontEnd;
|
2005-05-03 16:56:47 +02:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
BackEnd *backEnd;
|
2005-05-03 16:56:47 +02:00
|
|
|
private:
|
2005-02-26 00:00:49 +01:00
|
|
|
Status status() const { return _status; }
|
2006-04-23 00:45:01 +02:00
|
|
|
void setStatus(Status new_status) { _status = new_status; }
|
|
|
|
|
|
|
|
// Not sure what an activate() call on the CPU's proxy XC would mean...
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
virtual void activateContext(int thread_num, int delay);
|
|
|
|
virtual void suspendContext(int thread_num);
|
|
|
|
virtual void deallocateContext(int thread_num);
|
|
|
|
virtual void haltContext(int thread_num);
|
|
|
|
|
|
|
|
// statistics
|
|
|
|
virtual void regStats();
|
|
|
|
virtual void resetStats();
|
|
|
|
|
|
|
|
// number of simulated instructions
|
2006-04-23 00:45:01 +02:00
|
|
|
public:
|
2005-02-26 00:00:49 +01:00
|
|
|
Counter numInst;
|
|
|
|
Counter startNumInst;
|
2006-04-23 00:45:01 +02:00
|
|
|
// Stats::Scalar<> numInsts;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
virtual Counter totalInstructions() const
|
|
|
|
{
|
|
|
|
return numInst - startNumInst;
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
private:
|
2005-02-26 00:00:49 +01:00
|
|
|
// number of simulated memory references
|
2006-04-23 00:45:01 +02:00
|
|
|
// Stats::Scalar<> numMemRefs;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
// number of simulated loads
|
|
|
|
Counter numLoad;
|
|
|
|
Counter startNumLoad;
|
|
|
|
|
|
|
|
// number of idle cycles
|
|
|
|
Stats::Average<> notIdleFraction;
|
|
|
|
Stats::Formula idleFraction;
|
2005-05-03 16:56:47 +02:00
|
|
|
public:
|
|
|
|
|
2005-02-26 00:00:49 +01:00
|
|
|
virtual void serialize(std::ostream &os);
|
|
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
|
2005-08-30 19:18:54 +02:00
|
|
|
#if FULL_SYSTEM
|
2005-02-26 00:00:49 +01:00
|
|
|
bool validInstAddr(Addr addr) { return true; }
|
|
|
|
bool validDataAddr(Addr addr) { return true; }
|
|
|
|
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateInstReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return itb->translate(req);
|
|
|
|
}
|
|
|
|
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataReadReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return dtb->translate(req, false);
|
|
|
|
}
|
|
|
|
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataWriteReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
|
|
|
return dtb->translate(req, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
bool validInstAddr(Addr addr)
|
2006-04-23 00:45:01 +02:00
|
|
|
{ return true; }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
|
|
|
bool validDataAddr(Addr addr)
|
2006-04-23 00:45:01 +02:00
|
|
|
{ return true; }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
int getInstAsid() { return thread.asid; }
|
|
|
|
int getDataAsid() { return thread.asid; }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-24 23:10:06 +02:00
|
|
|
Fault dummyTranslation(MemReqPtr &req)
|
|
|
|
{
|
|
|
|
#if 0
|
|
|
|
assert((req->vaddr >> 48 & 0xffff) == 0);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// put the asid in the upper 16 bits of the paddr
|
|
|
|
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
|
|
|
|
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
/** Translates instruction requestion in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateInstReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
2006-04-24 23:10:06 +02:00
|
|
|
return dummyTranslation(req);
|
2005-02-26 00:00:49 +01:00
|
|
|
}
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
/** Translates data read request in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataReadReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
2006-04-24 23:10:06 +02:00
|
|
|
return dummyTranslation(req);
|
2005-02-26 00:00:49 +01:00
|
|
|
}
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
/** Translates data write request in syscall emulation mode. */
|
2006-02-22 02:10:40 +01:00
|
|
|
Fault translateDataWriteReq(MemReqPtr &req)
|
2005-02-26 00:00:49 +01:00
|
|
|
{
|
2006-04-24 23:10:06 +02:00
|
|
|
return dummyTranslation(req);
|
2005-02-26 00:00:49 +01:00
|
|
|
}
|
|
|
|
#endif
|
2006-04-24 23:10:06 +02:00
|
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/** Old CPU read from memory function. No longer used. */
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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// panic("CPU READ NOT IMPLEMENTED W/NEW MEMORY\n");
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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#endif
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Fault error;
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if (req->flags & LOCKED) {
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// lockAddr = req->paddr;
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
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lockAddrList.insert(req->paddr);
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2006-04-24 23:10:06 +02:00
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lockFlag = true;
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}
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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2006-04-23 00:45:01 +02:00
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/** CPU read function, forwards read to LSQ. */
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2005-02-26 00:00:49 +01:00
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template <class T>
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2006-04-23 00:45:01 +02:00
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Fault read(MemReqPtr &req, T &data, int load_idx)
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{
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return backEnd->read(req, data, load_idx);
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}
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2005-02-26 00:00:49 +01:00
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2006-04-24 23:10:06 +02:00
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/** Old CPU write to memory function. No longer used. */
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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xc = req->xc;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->execContexts.size(); i++){
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xc = this->system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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#endif
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if (req->flags & LOCKED) {
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if (req->flags & UNCACHEABLE) {
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req->result = 2;
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} else {
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if (this->lockFlag/* && this->lockAddr == req->paddr*/) {
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Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
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if (lockAddrList.find(req->paddr) !=
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lockAddrList.end()) {
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req->result = 1;
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} else {
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req->result = 0;
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return NoFault;
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}
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2006-04-24 23:10:06 +02:00
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} else {
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req->result = 0;
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return NoFault;
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}
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}
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}
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return this->mem->write(req, (T)htog(data));
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}
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2006-04-23 00:45:01 +02:00
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/** CPU write function, forwards write to LSQ. */
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2005-02-26 00:00:49 +01:00
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template <class T>
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2006-04-23 00:45:01 +02:00
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|
Fault write(MemReqPtr &req, T &data, int store_idx)
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{
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return backEnd->write(req, data, store_idx);
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}
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2005-02-26 00:00:49 +01:00
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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|
2006-02-22 02:10:40 +01:00
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Fault copySrcTranslate(Addr src);
|
2005-02-26 00:00:49 +01:00
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|
2006-02-22 02:10:40 +01:00
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Fault copy(Addr dest);
|
2005-02-26 00:00:49 +01:00
|
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InstSeqNum globalSeqNum;
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public:
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2006-04-23 00:45:01 +02:00
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void squashFromXC();
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2005-02-26 00:00:49 +01:00
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|
2006-04-23 00:45:01 +02:00
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// @todo: This can be a useful debug function. Implement it.
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void dumpInsts() { frontEnd->dumpInsts(); }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2005-08-30 19:18:54 +02:00
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|
|
#if FULL_SYSTEM
|
2006-04-23 00:45:01 +02:00
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|
Fault hwrei();
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|
|
int readIntrFlag() { return thread.regs.intrflag; }
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|
|
void setIntrFlag(int val) { thread.regs.intrflag = val; }
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|
|
bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
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bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
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|
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bool simPalCheck(int palFunc);
|
2006-04-23 01:10:39 +02:00
|
|
|
void processInterrupts();
|
2005-02-26 00:00:49 +01:00
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|
#else
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2006-04-23 00:45:01 +02:00
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|
|
void syscall();
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|
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void setSyscallReturn(SyscallReturn return_value, int tid);
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2005-02-26 00:00:49 +01:00
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#endif
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|
|
|
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
ExecContext *xcBase() { return xcProxy; }
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
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|
|
bool decoupledFrontEnd;
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|
|
|
struct CommStruct {
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|
|
|
InstSeqNum doneSeqNum;
|
|
|
|
InstSeqNum nonSpecSeqNum;
|
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|
|
bool uncached;
|
|
|
|
unsigned lqIdx;
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
bool stall;
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|
|
};
|
|
|
|
TimeBuffer<CommStruct> comm;
|
2006-04-24 23:10:06 +02:00
|
|
|
|
|
|
|
bool lockFlag;
|
2006-04-24 23:40:00 +02:00
|
|
|
|
|
|
|
Stats::Scalar<> quiesceCycles;
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
|
|
|
|
Checker<DynInstPtr> *checker;
|
2006-04-23 00:45:01 +02:00
|
|
|
};
|
2005-02-26 00:00:49 +01:00
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
#endif // __CPU_OZONE_CPU_HH__
|