gem5/tests/configs/simple-timing.py

# Copyright (c) 2006 The Regents of The University of Michigan
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# Authors: Steve Reinhardt

import m5
from m5.objects import *

class MyCache(BaseCache):
    assoc = 2
    block_size = 64
    latency = 1
    mshrs = 10
    tgts_per_mshr = 5

cpu = TimingSimpleCPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                              MyCache(size = '2MB'))
cpu.mem = cpu.dcache
cpu.mem = cpu.dcache
system = System(cpu = cpu,
                physmem = PhysicalMemory(),
                membus = Bus())
system.physmem.port = system.membus.port
cpu.connectMemPorts(system.membus)

root = Root(system = system)