2006-08-16 20:42:44 +02:00
|
|
|
# Copyright (c) 2006 The Regents of The University of Michigan
|
|
|
|
# All rights reserved.
|
|
|
|
#
|
|
|
|
# Redistribution and use in source and binary forms, with or without
|
|
|
|
# modification, are permitted provided that the following conditions are
|
|
|
|
# met: redistributions of source code must retain the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer;
|
|
|
|
# redistributions in binary form must reproduce the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
|
|
# documentation and/or other materials provided with the distribution;
|
|
|
|
# neither the name of the copyright holders nor the names of its
|
|
|
|
# contributors may be used to endorse or promote products derived from
|
|
|
|
# this software without specific prior written permission.
|
|
|
|
#
|
|
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
#
|
|
|
|
# Authors: Ali Saidi
|
|
|
|
|
|
|
|
import optparse, os, sys
|
|
|
|
|
|
|
|
import m5
|
|
|
|
from m5.objects import *
|
|
|
|
m5.AddToPath('../common')
|
|
|
|
from FSConfig import *
|
|
|
|
from SysPaths import *
|
|
|
|
from Benchmarks import *
|
2006-10-27 22:32:26 +02:00
|
|
|
import Simulation
|
2006-10-30 22:51:46 +01:00
|
|
|
from Caches import *
|
2006-08-16 20:42:44 +02:00
|
|
|
|
2006-08-29 23:36:35 +02:00
|
|
|
if not m5.build_env['FULL_SYSTEM']:
|
|
|
|
m5.panic("This script requires full-system mode (ALPHA_FS).")
|
|
|
|
|
2006-10-30 20:01:34 +01:00
|
|
|
# Get paths we might need. It's expected this file is in m5/configs/example.
|
|
|
|
config_path = os.path.dirname(os.path.abspath(__file__))
|
|
|
|
config_root = os.path.dirname(config_path)
|
|
|
|
|
2006-08-16 20:42:44 +02:00
|
|
|
parser = optparse.OptionParser()
|
|
|
|
|
2006-10-24 00:07:51 +02:00
|
|
|
# Benchmark options
|
2006-11-16 00:22:15 +01:00
|
|
|
parser.add_option("--l2cache", action="store_true")
|
2006-08-16 20:42:44 +02:00
|
|
|
parser.add_option("--dual", action="store_true",
|
|
|
|
help="Simulate two systems attached with an ethernet link")
|
|
|
|
parser.add_option("-b", "--benchmark", action="store", type="string",
|
|
|
|
dest="benchmark",
|
|
|
|
help="Specify the benchmark to run. Available benchmarks: %s"\
|
2006-10-06 06:42:39 +02:00
|
|
|
% DefinedBenchmarks)
|
2006-10-24 00:07:51 +02:00
|
|
|
|
|
|
|
# Metafile options
|
2006-08-17 04:17:23 +02:00
|
|
|
parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
|
2006-10-06 06:42:39 +02:00
|
|
|
help="Specify the filename to dump a pcap capture of the" \
|
|
|
|
"ethernet traffic")
|
2006-10-24 00:07:51 +02:00
|
|
|
|
2006-10-30 20:01:34 +01:00
|
|
|
execfile(os.path.join(config_root, "common", "Options.py"))
|
2006-10-24 00:07:51 +02:00
|
|
|
|
2006-08-16 20:42:44 +02:00
|
|
|
(options, args) = parser.parse_args()
|
|
|
|
|
|
|
|
if args:
|
|
|
|
print "Error: script doesn't take any positional arguments"
|
|
|
|
sys.exit(1)
|
|
|
|
|
2006-10-24 00:07:51 +02:00
|
|
|
# driver system CPU is always simple... note this is an assignment of
|
2006-10-17 20:08:49 +02:00
|
|
|
# a class, not an instance.
|
2006-10-24 00:07:51 +02:00
|
|
|
DriveCPUClass = AtomicSimpleCPU
|
|
|
|
drive_mem_mode = 'atomic'
|
2006-10-17 20:08:49 +02:00
|
|
|
|
2006-11-02 01:25:09 +01:00
|
|
|
# system under test can be any CPU
|
|
|
|
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
|
2006-08-16 20:42:44 +02:00
|
|
|
|
2006-10-24 00:07:51 +02:00
|
|
|
TestCPUClass.clock = '2GHz'
|
|
|
|
DriveCPUClass.clock = '2GHz'
|
2006-08-16 20:42:44 +02:00
|
|
|
|
|
|
|
if options.benchmark:
|
2006-10-17 20:08:49 +02:00
|
|
|
try:
|
|
|
|
bm = Benchmarks[options.benchmark]
|
|
|
|
except KeyError:
|
2006-08-16 20:42:44 +02:00
|
|
|
print "Error benchmark %s has not been defined." % options.benchmark
|
|
|
|
print "Valid benchmarks are: %s" % DefinedBenchmarks
|
|
|
|
sys.exit(1)
|
|
|
|
else:
|
|
|
|
if options.dual:
|
2006-10-17 20:08:49 +02:00
|
|
|
bm = [SysConfig(), SysConfig()]
|
2006-08-16 20:42:44 +02:00
|
|
|
else:
|
2006-10-17 20:08:49 +02:00
|
|
|
bm = [SysConfig()]
|
|
|
|
|
2006-12-05 01:37:50 +01:00
|
|
|
if m5.build_env['TARGET_ISA'] == "alpha":
|
|
|
|
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
|
|
|
|
elif m5.build_env['TARGET_ISA'] == "sparc":
|
|
|
|
test_sys = makeSparcSystem(test_mem_mode, bm[0])
|
|
|
|
else:
|
|
|
|
m5.panic("incapable of building non-alpha or non-sparc full system!")
|
|
|
|
|
2006-10-18 06:15:11 +02:00
|
|
|
np = options.num_cpus
|
2006-11-16 00:22:15 +01:00
|
|
|
|
|
|
|
if options.l2cache:
|
|
|
|
test_sys.l2 = L2Cache(size = '2MB')
|
|
|
|
test_sys.tol2bus = Bus()
|
|
|
|
test_sys.l2.cpu_side = test_sys.tol2bus.port
|
|
|
|
test_sys.l2.mem_side = test_sys.membus.port
|
|
|
|
|
2006-10-24 00:07:51 +02:00
|
|
|
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
|
2006-10-18 06:15:11 +02:00
|
|
|
for i in xrange(np):
|
2006-11-09 21:05:13 +01:00
|
|
|
if options.caches:
|
2006-10-27 22:32:26 +02:00
|
|
|
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
|
2006-10-30 22:51:46 +01:00
|
|
|
L1Cache(size = '64kB'))
|
2006-11-16 00:22:15 +01:00
|
|
|
|
|
|
|
if options.l2cache:
|
|
|
|
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
|
|
|
|
else:
|
|
|
|
test_sys.cpu[i].connectMemPorts(test_sys.membus)
|
2006-08-16 20:42:44 +02:00
|
|
|
|
|
|
|
if len(bm) == 2:
|
2006-12-05 01:37:50 +01:00
|
|
|
if m5.build_env['TARGET_ISA'] == 'alpha':
|
|
|
|
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
|
|
|
|
elif m5.build_env['TARGET_ISA'] == 'sparc':
|
|
|
|
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
|
2006-10-24 00:07:51 +02:00
|
|
|
drive_sys.cpu = DriveCPUClass(cpu_id=0)
|
|
|
|
drive_sys.cpu.connectMemPorts(drive_sys.membus)
|
|
|
|
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
|
2006-08-16 20:42:44 +02:00
|
|
|
elif len(bm) == 1:
|
2006-10-24 00:07:51 +02:00
|
|
|
root = Root(clock = '1THz', system = test_sys)
|
2006-08-16 20:42:44 +02:00
|
|
|
else:
|
|
|
|
print "Error I don't know how to create more than 2 systems."
|
|
|
|
sys.exit(1)
|
|
|
|
|
2006-11-02 01:25:09 +01:00
|
|
|
Simulation.run(options, root, test_sys, FutureClass)
|