2004-02-06 00:23:16 +01:00
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/*
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2005-01-30 22:58:39 +01:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-02-06 00:23:16 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2004-01-22 02:14:10 +01:00
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/* @file
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2004-01-26 19:26:34 +01:00
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* Tsunami I/O including PIC, PIT, RTC, DMA
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2004-01-22 02:14:10 +01:00
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*/
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2004-01-26 19:26:34 +01:00
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#include <sys/time.h>
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2004-01-22 02:14:10 +01:00
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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2004-01-22 06:36:26 +01:00
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#include "dev/tsunami_io.hh"
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2004-01-22 02:14:10 +01:00
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#include "dev/tsunami.hh"
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2004-06-10 19:30:58 +02:00
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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2004-01-22 02:14:10 +01:00
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#include "sim/builder.hh"
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2004-01-28 03:36:46 +01:00
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#include "dev/tsunami_cchip.hh"
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2004-06-10 19:30:58 +02:00
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#include "dev/tsunamireg.h"
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2005-01-30 22:58:39 +01:00
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#include "dev/rtcreg.h"
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2004-06-10 19:30:58 +02:00
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#include "mem/functional_mem/memory_control.hh"
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2004-01-22 02:14:10 +01:00
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using namespace std;
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2004-01-26 19:26:34 +01:00
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#define UNIX_YEAR_OFFSET 52
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// Timer Event for Periodic interrupt of RTC
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2004-01-28 03:36:46 +01:00
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TsunamiIO::RTCEvent::RTCEvent(Tsunami* t)
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: Event(&mainEventQueue), tsunami(t)
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2004-01-23 19:01:32 +01:00
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{
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2004-01-26 19:26:34 +01:00
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DPRINTF(MC146818, "RTC Event Initilizing\n");
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schedule(curTick + ticksPerSecond/RTC_RATE);
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2004-01-23 19:01:32 +01:00
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}
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void
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TsunamiIO::RTCEvent::process()
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{
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2004-01-29 00:12:52 +01:00
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DPRINTF(MC146818, "RTC Timer Interrupt\n");
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2004-01-26 19:26:34 +01:00
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schedule(curTick + ticksPerSecond/RTC_RATE);
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//Actually interrupt the processor here
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2004-02-20 22:51:19 +01:00
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tsunami->cchip->postRTC();
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2004-01-23 19:01:32 +01:00
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}
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const char *
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TsunamiIO::RTCEvent::description()
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{
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2004-01-26 19:26:34 +01:00
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return "tsunami RTC 1024Hz interrupt";
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2004-01-23 19:01:32 +01:00
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}
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2004-01-22 02:14:10 +01:00
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2004-06-17 00:20:10 +02:00
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void
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TsunamiIO::RTCEvent::serialize(std::ostream &os)
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{
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Tick time = when();
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SERIALIZE_SCALAR(time);
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}
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void
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TsunamiIO::RTCEvent::unserialize(Checkpoint *cp, const std::string §ion)
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{
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Tick time;
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UNSERIALIZE_SCALAR(time);
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reschedule(time);
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}
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2004-01-26 19:26:34 +01:00
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// Timer Event for PIT Timers
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2004-01-23 01:02:07 +01:00
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TsunamiIO::ClockEvent::ClockEvent()
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: Event(&mainEventQueue)
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{
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2005-03-29 14:55:44 +02:00
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/* This is the PIT Tick Rate. A constant for the 8254 timer. The
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* Tsunami platform has one of these cycle counters on the Cypress
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* South Bridge and it is used by linux for estimating the cycle
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* frequency of the machine it is running on. --Ali
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*/
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interval = (Tick)(Clock::Float::s / 1193180.0);
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2004-01-23 01:02:07 +01:00
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DPRINTF(Tsunami, "Clock Event Initilizing\n");
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mode = 0;
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}
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void
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TsunamiIO::ClockEvent::process()
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{
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DPRINTF(Tsunami, "Timer Interrupt\n");
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if (mode == 0)
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2004-02-06 00:23:16 +01:00
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status = 0x20; // set bit that linux is looking for
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2004-01-23 01:02:07 +01:00
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else
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schedule(curTick + interval);
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}
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void
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TsunamiIO::ClockEvent::Program(int count)
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{
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DPRINTF(Tsunami, "Timer set to curTick + %d\n", count);
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2005-03-29 14:55:44 +02:00
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schedule(curTick + count * interval);
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2004-01-23 01:02:07 +01:00
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status = 0;
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}
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const char *
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TsunamiIO::ClockEvent::description()
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{
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return "tsunami 8254 Interval timer";
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}
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void
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TsunamiIO::ClockEvent::ChangeMode(uint8_t md)
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{
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mode = md;
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}
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uint8_t
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TsunamiIO::ClockEvent::Status()
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{
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return status;
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}
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2004-06-17 00:20:10 +02:00
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void
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TsunamiIO::ClockEvent::serialize(std::ostream &os)
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{
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2004-06-17 01:47:07 +02:00
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Tick time = scheduled() ? when() : 0;
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2004-06-17 00:20:10 +02:00
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SERIALIZE_SCALAR(time);
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SERIALIZE_SCALAR(status);
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SERIALIZE_SCALAR(mode);
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SERIALIZE_SCALAR(interval);
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}
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void
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TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string §ion)
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{
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Tick time;
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UNSERIALIZE_SCALAR(time);
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UNSERIALIZE_SCALAR(status);
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UNSERIALIZE_SCALAR(mode);
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UNSERIALIZE_SCALAR(interval);
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2004-06-17 01:47:07 +02:00
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if (time)
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schedule(time);
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2004-06-17 00:20:10 +02:00
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}
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2004-01-28 03:36:46 +01:00
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TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
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2004-07-13 04:58:22 +02:00
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Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
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Tick pio_latency)
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2005-01-15 10:12:25 +01:00
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: PioDevice(name, t), addr(a), tsunami(t), rtc(t)
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2004-01-22 02:14:10 +01:00
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{
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2004-10-22 07:34:40 +02:00
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mmu->add_child(this, RangeSize(addr, size));
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2004-02-10 06:19:43 +01:00
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2004-06-10 19:30:58 +02:00
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiIO::cacheAccess);
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2004-10-22 07:34:40 +02:00
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pioInterface->addAddrRange(RangeSize(addr, size));
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2004-07-13 04:58:22 +02:00
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pioLatency = pio_latency * bus->clockRatio;
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2004-06-10 19:30:58 +02:00
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}
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2004-02-06 00:23:16 +01:00
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// set the back pointer from tsunami to myself
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tsunami->io = this;
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2004-01-23 01:02:07 +01:00
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timerData = 0;
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2004-01-26 19:26:34 +01:00
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set_time(init_time == 0 ? time(NULL) : init_time);
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uip = 1;
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2004-01-29 01:18:29 +01:00
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picr = 0;
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picInterrupting = false;
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2004-01-26 19:26:34 +01:00
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}
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void
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TsunamiIO::set_time(time_t t)
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{
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gmtime_r(&t, &tm);
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DPRINTFN("Real-time clock set to %s", asctime(&tm));
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2004-01-22 02:14:10 +01:00
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}
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Fault
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2004-02-03 22:59:40 +01:00
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TsunamiIO::read(MemReqPtr &req, uint8_t *data)
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2004-01-22 02:14:10 +01:00
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{
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2004-01-22 06:36:26 +01:00
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DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
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2004-01-22 02:14:10 +01:00
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req->vaddr, req->size, req->vaddr & 0xfff);
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2004-11-13 20:01:38 +01:00
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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2004-05-14 23:34:15 +02:00
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2004-01-23 01:02:07 +01:00
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switch(req->size) {
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2004-02-06 00:23:16 +01:00
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case sizeof(uint8_t):
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switch(daddr) {
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2004-05-14 23:34:15 +02:00
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 64bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint8_t*)data = picr;
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return No_Fault;
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case TSDEV_PIC2_ISR:
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// PIC2 not implemnted... just return 0
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*(uint8_t*)data = 0x00;
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return No_Fault;
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2004-02-06 00:23:16 +01:00
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case TSDEV_TMR_CTL:
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*(uint8_t*)data = timer2.Status();
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return No_Fault;
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case TSDEV_RTC_DATA:
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switch(RTCAddress) {
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2005-01-30 22:58:39 +01:00
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case RTC_CNTRL_REGA:
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2004-02-06 00:23:16 +01:00
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*(uint8_t*)data = uip << 7 | 0x26;
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uip = !uip;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_CNTRL_REGB:
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2004-02-06 00:23:16 +01:00
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// DM and 24/12 and UIE
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*(uint8_t*)data = 0x46;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_CNTRL_REGC:
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2004-02-06 00:23:16 +01:00
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// If we want to support RTC user access in linux
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// This won't work, but for now it's fine
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*(uint8_t*)data = 0x00;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_CNTRL_REGD:
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2004-02-06 00:23:16 +01:00
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panic("RTC Control Register D not implemented");
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2005-01-30 22:58:39 +01:00
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case RTC_SEC:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_sec;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_MIN:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_min;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_HR:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_hour;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_DOW:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_wday;
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return No_Fault;
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2005-01-30 22:58:39 +01:00
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case RTC_DOM:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_mday;
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2005-01-30 22:58:39 +01:00
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case RTC_MON:
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2004-02-06 00:23:16 +01:00
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*(uint8_t *)data = tm.tm_mon + 1;
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return No_Fault;
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case RTC_YEAR:
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*(uint8_t *)data = tm.tm_year - UNIX_YEAR_OFFSET;
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return No_Fault;
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default:
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panic("Unknown RTC Address\n");
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2004-01-23 01:02:07 +01:00
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}
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2004-02-06 00:23:16 +01:00
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default:
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panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
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}
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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2004-05-14 23:34:15 +02:00
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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2004-02-06 00:23:16 +01:00
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case sizeof(uint64_t):
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2004-05-14 23:34:15 +02:00
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switch(daddr) {
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case TSDEV_PIC1_ISR:
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// !!! If this is modified 8bit case needs to be too
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// Pal code has to do a 64 bit physical read because there is
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// no load physical byte instruction
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*(uint64_t*)data = (uint64_t)picr;
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return No_Fault;
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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}
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2004-02-06 00:23:16 +01:00
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default:
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panic("I/O Read - invalid size - va %#x size %d\n",
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req->vaddr, req->size);
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2004-01-23 01:02:07 +01:00
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}
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2004-02-06 00:23:16 +01:00
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panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
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2004-01-22 02:14:10 +01:00
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return No_Fault;
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}
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Fault
|
2004-02-03 22:59:40 +01:00
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TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
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2004-01-22 02:14:10 +01:00
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{
|
2004-06-17 00:20:10 +02:00
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#if TRACING_ON
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2004-01-30 21:24:50 +01:00
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uint8_t dt = *(uint8_t*)data;
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uint64_t dt64 = dt;
|
2004-06-17 00:20:10 +02:00
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#endif
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2004-01-30 21:24:50 +01:00
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|
|
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
|
|
|
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-11-13 20:01:38 +01:00
|
|
|
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
|
2004-01-22 06:08:48 +01:00
|
|
|
|
|
|
|
switch(req->size) {
|
2004-02-06 00:23:16 +01:00
|
|
|
case sizeof(uint8_t):
|
|
|
|
switch(daddr) {
|
|
|
|
case TSDEV_PIC1_MASK:
|
2004-05-14 23:34:15 +02:00
|
|
|
mask1 = ~(*(uint8_t*)data);
|
2004-02-06 00:23:16 +01:00
|
|
|
if ((picr & mask1) && !picInterrupting) {
|
|
|
|
picInterrupting = true;
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->postDRIR(55);
|
2004-02-06 00:23:16 +01:00
|
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
|
|
}
|
2004-05-14 23:34:15 +02:00
|
|
|
if ((!(picr & mask1)) && picInterrupting) {
|
|
|
|
picInterrupting = false;
|
|
|
|
tsunami->cchip->clearDRIR(55);
|
|
|
|
DPRINTF(Tsunami, "clearing pic interrupt\n");
|
|
|
|
}
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_PIC2_MASK:
|
|
|
|
mask2 = *(uint8_t*)data;
|
|
|
|
//PIC2 Not implemented to interrupt
|
|
|
|
return No_Fault;
|
2004-05-14 23:34:15 +02:00
|
|
|
case TSDEV_PIC1_ACK:
|
|
|
|
// clear the interrupt on the PIC
|
|
|
|
picr &= ~(1 << (*(uint8_t*)data & 0xF));
|
|
|
|
if (!(picr & mask1))
|
|
|
|
tsunami->cchip->clearDRIR(55);
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_PIC2_ACK:
|
|
|
|
return No_Fault;
|
2004-02-06 00:23:16 +01:00
|
|
|
case TSDEV_DMA1_RESET:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_RESET:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA1_MODE:
|
|
|
|
mode1 = *(uint8_t*)data;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA2_MODE:
|
|
|
|
mode2 = *(uint8_t*)data;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_DMA1_MASK:
|
|
|
|
case TSDEV_DMA2_MASK:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR_CTL:
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR2_CTL:
|
|
|
|
if ((*(uint8_t*)data & 0x30) != 0x30)
|
|
|
|
panic("Only L/M write supported\n");
|
|
|
|
|
|
|
|
switch(*(uint8_t*)data >> 6) {
|
|
|
|
case 0:
|
|
|
|
timer0.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
timer2.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Read Back Command not implemented\n");
|
|
|
|
}
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR2_DATA:
|
|
|
|
/* two writes before we actually start the Timer
|
|
|
|
so I set a flag in the timerData */
|
|
|
|
if(timerData & 0x1000) {
|
|
|
|
timerData &= 0x1000;
|
|
|
|
timerData += *(uint8_t*)data << 8;
|
|
|
|
timer2.Program(timerData);
|
|
|
|
} else {
|
|
|
|
timerData = *(uint8_t*)data;
|
|
|
|
timerData |= 0x1000;
|
|
|
|
}
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_TMR0_DATA:
|
|
|
|
/* two writes before we actually start the Timer
|
|
|
|
so I set a flag in the timerData */
|
|
|
|
if(timerData & 0x1000) {
|
|
|
|
timerData &= 0x1000;
|
|
|
|
timerData += *(uint8_t*)data << 8;
|
|
|
|
timer0.Program(timerData);
|
|
|
|
} else {
|
|
|
|
timerData = *(uint8_t*)data;
|
|
|
|
timerData |= 0x1000;
|
2004-01-22 06:08:48 +01:00
|
|
|
}
|
2004-02-06 00:23:16 +01:00
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_RTC_ADDR:
|
|
|
|
RTCAddress = *(uint8_t*)data;
|
|
|
|
return No_Fault;
|
|
|
|
case TSDEV_RTC_DATA:
|
|
|
|
panic("RTC Write not implmented (rtc.o won't work)\n");
|
|
|
|
default:
|
|
|
|
panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
|
|
|
|
}
|
|
|
|
case sizeof(uint16_t):
|
|
|
|
case sizeof(uint32_t):
|
|
|
|
case sizeof(uint64_t):
|
|
|
|
default:
|
|
|
|
panic("I/O Write - invalid size - va %#x size %d\n",
|
|
|
|
req->vaddr, req->size);
|
2004-01-22 06:08:48 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 02:14:10 +01:00
|
|
|
|
|
|
|
return No_Fault;
|
|
|
|
}
|
|
|
|
|
2004-01-29 01:18:29 +01:00
|
|
|
void
|
|
|
|
TsunamiIO::postPIC(uint8_t bitvector)
|
|
|
|
{
|
|
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
|
|
picr |= bitvector;
|
2004-05-14 23:34:15 +02:00
|
|
|
if (picr & mask1) {
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->postDRIR(55);
|
2004-01-29 01:18:29 +01:00
|
|
|
DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TsunamiIO::clearPIC(uint8_t bitvector)
|
|
|
|
{
|
|
|
|
//PIC2 Is not implemented, because nothing of interest there
|
|
|
|
picr &= ~bitvector;
|
|
|
|
if (!(picr & mask1)) {
|
2004-02-16 05:56:44 +01:00
|
|
|
tsunami->cchip->clearDRIR(55);
|
2004-01-29 01:18:29 +01:00
|
|
|
DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-06-10 19:30:58 +02:00
|
|
|
Tick
|
|
|
|
TsunamiIO::cacheAccess(MemReqPtr &req)
|
|
|
|
{
|
2004-07-13 04:58:22 +02:00
|
|
|
return curTick + pioLatency;
|
2004-06-10 19:30:58 +02:00
|
|
|
}
|
|
|
|
|
2004-01-22 02:14:10 +01:00
|
|
|
void
|
2004-01-22 06:36:26 +01:00
|
|
|
TsunamiIO::serialize(std::ostream &os)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-02-11 21:32:30 +01:00
|
|
|
SERIALIZE_SCALAR(timerData);
|
|
|
|
SERIALIZE_SCALAR(uip);
|
2004-06-04 20:26:17 +02:00
|
|
|
SERIALIZE_SCALAR(mask1);
|
|
|
|
SERIALIZE_SCALAR(mask2);
|
|
|
|
SERIALIZE_SCALAR(mode1);
|
|
|
|
SERIALIZE_SCALAR(mode2);
|
2004-02-11 21:32:30 +01:00
|
|
|
SERIALIZE_SCALAR(picr);
|
|
|
|
SERIALIZE_SCALAR(picInterrupting);
|
2004-06-04 20:26:17 +02:00
|
|
|
SERIALIZE_SCALAR(RTCAddress);
|
2004-02-11 21:32:30 +01:00
|
|
|
|
2004-06-17 01:47:07 +02:00
|
|
|
// Serialize the timers
|
|
|
|
nameOut(os, csprintf("%s.timer0", name()));
|
|
|
|
timer0.serialize(os);
|
|
|
|
nameOut(os, csprintf("%s.timer2", name()));
|
|
|
|
timer2.serialize(os);
|
|
|
|
nameOut(os, csprintf("%s.rtc", name()));
|
|
|
|
rtc.serialize(os);
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2004-01-22 06:36:26 +01:00
|
|
|
TsunamiIO::unserialize(Checkpoint *cp, const std::string §ion)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-02-11 21:32:30 +01:00
|
|
|
UNSERIALIZE_SCALAR(timerData);
|
|
|
|
UNSERIALIZE_SCALAR(uip);
|
2004-06-04 20:26:17 +02:00
|
|
|
UNSERIALIZE_SCALAR(mask1);
|
|
|
|
UNSERIALIZE_SCALAR(mask2);
|
|
|
|
UNSERIALIZE_SCALAR(mode1);
|
|
|
|
UNSERIALIZE_SCALAR(mode2);
|
2004-02-11 21:32:30 +01:00
|
|
|
UNSERIALIZE_SCALAR(picr);
|
|
|
|
UNSERIALIZE_SCALAR(picInterrupting);
|
2004-06-04 20:26:17 +02:00
|
|
|
UNSERIALIZE_SCALAR(RTCAddress);
|
2004-06-17 01:47:07 +02:00
|
|
|
|
|
|
|
// Unserialize the timers
|
|
|
|
timer0.unserialize(cp, csprintf("%s.timer0", section));
|
|
|
|
timer2.unserialize(cp, csprintf("%s.timer2", section));
|
|
|
|
rtc.unserialize(cp, csprintf("%s.rtc", section));
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-28 03:36:46 +01:00
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
2004-01-26 19:26:34 +01:00
|
|
|
Param<time_t> time;
|
2004-01-22 02:14:10 +01:00
|
|
|
SimObjectParam<MemoryController *> mmu;
|
|
|
|
Param<Addr> addr;
|
2004-06-10 19:30:58 +02:00
|
|
|
SimObjectParam<Bus*> io_bus;
|
2004-07-13 04:58:22 +02:00
|
|
|
Param<Tick> pio_latency;
|
2004-06-10 19:30:58 +02:00
|
|
|
SimObjectParam<HierParams *> hier;
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-28 03:36:46 +01:00
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
2004-01-26 19:26:34 +01:00
|
|
|
INIT_PARAM_DFLT(time, "System time to use "
|
|
|
|
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
|
2004-01-22 02:14:10 +01:00
|
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
2004-06-10 19:30:58 +02:00
|
|
|
INIT_PARAM(addr, "Device Address"),
|
|
|
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
2004-07-13 04:58:22 +02:00
|
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
2004-06-10 19:30:58 +02:00
|
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
CREATE_SIM_OBJECT(TsunamiIO)
|
2004-01-22 02:14:10 +01:00
|
|
|
{
|
2004-06-10 19:30:58 +02:00
|
|
|
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
|
2004-07-13 04:58:22 +02:00
|
|
|
io_bus, pio_latency);
|
2004-01-22 02:14:10 +01:00
|
|
|
}
|
|
|
|
|
2004-01-22 06:36:26 +01:00
|
|
|
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|