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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

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stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
host_inst_rate 170274 # Simulator instruction rate (inst/s)
host_op_rate 170274 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 22048637 # Simulator tick rate (ticks/s)
host_mem_usage 246052 # Number of bytes of host memory used
host_seconds 3.98 # Real time elapsed on the host
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
sim_insts 677327 # Number of instructions simulated
sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.throughput 407903588 # Throughput (bytes/s)
system.membus.data_through_bus 35776 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use
system.l2c.tags.total_refs 1220 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
system.toL2Bus.data_through_bus 166080 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 175326 # Number of instructions committed
system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
system.cpu0.num_int_insts 120376 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 82397 # number of memory refs
system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 175415 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu0.icache.tags.replacements 215 # number of replacements
system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
system.cpu0.icache.overall_hits::total 174921 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 173295 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 167398 # Number of instructions committed
system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
system.cpu1.num_int_insts 109926 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 53394 # number of memory refs
system.cpu1.num_load_insts 40652 # Number of load instructions
system.cpu1.num_store_insts 12742 # Number of store instructions
system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu1.icache.tags.replacements 278 # number of replacements
system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
system.cpu1.icache.overall_hits::total 167072 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
system.cpu1.icache.overall_misses::total 358 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
system.cpu1.dcache.overall_misses::total 280 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 173295 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 167334 # Number of instructions committed
system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
system.cpu2.num_int_insts 113333 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu2.num_mem_refs 58537 # number of memory refs
system.cpu2.num_load_insts 42362 # Number of load instructions
system.cpu2.num_store_insts 16175 # Number of store instructions
system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu2.icache.tags.replacements 278 # number of replacements
system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
system.cpu2.icache.overall_hits::total 167008 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
system.cpu2.icache.overall_misses::total 358 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
system.cpu2.dcache.overall_misses::total 269 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173294 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 167269 # Number of instructions committed
system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
system.cpu3.num_int_insts 111554 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 55900 # number of memory refs
system.cpu3.num_load_insts 41466 # Number of load instructions
system.cpu3.num_store_insts 14434 # Number of store instructions
system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu3.icache.tags.replacements 279 # number of replacements
system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
system.cpu3.icache.overall_hits::total 166942 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy
stats: Update stats for fixed simple-atomic-mp config This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31 13:39:45 +01:00
system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
system.cpu3.dcache.overall_misses::total 259 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink