2004-02-04 21:03:50 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-02-04 21:03:50 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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* Nathan Binkert
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2004-02-04 21:03:50 +01:00
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*/
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/* @file
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2004-03-22 22:50:09 +01:00
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* Interface for devices using PCI configuration
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2004-02-04 21:03:50 +01:00
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*/
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2004-11-13 21:45:22 +01:00
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#ifndef __DEV_PCIDEV_HH__
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#define __DEV_PCIDEV_HH__
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2004-02-04 21:03:50 +01:00
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2007-01-27 00:48:51 +01:00
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#include <cstring>
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2012-05-23 15:15:45 +02:00
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#include "dev/dma_device.hh"
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2004-11-13 21:45:22 +01:00
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#include "dev/pcireg.h"
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#include "dev/platform.hh"
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2007-07-24 06:51:38 +02:00
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#include "params/PciDevice.hh"
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2006-10-20 08:38:45 +02:00
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#include "sim/byteswap.hh"
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2004-02-05 01:56:24 +01:00
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2005-08-15 22:59:58 +02:00
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#define BAR_IO_MASK 0x3
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#define BAR_MEM_MASK 0xF
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#define BAR_IO_SPACE_BIT 0x1
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#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
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#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
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2004-05-30 23:45:46 +02:00
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2006-07-06 20:41:01 +02:00
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2004-02-05 01:56:24 +01:00
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/**
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2006-08-28 19:28:31 +02:00
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* PCI device, base implementation is only config space.
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2004-02-04 21:03:50 +01:00
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*/
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2004-03-22 22:50:09 +01:00
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class PciDev : public DmaDevice
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2004-02-04 21:03:50 +01:00
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{
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2006-08-31 01:24:26 +02:00
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class PciConfigPort : public SimpleTimingPort
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2004-11-13 21:45:22 +01:00
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{
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2006-07-06 20:41:01 +02:00
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protected:
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PciDev *device;
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2006-10-20 09:10:12 +02:00
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virtual Tick recvAtomic(PacketPtr pkt);
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2006-07-06 20:41:01 +02:00
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2012-07-09 18:35:34 +02:00
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virtual AddrRangeList getAddrRanges() const;
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2006-07-06 20:41:01 +02:00
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2006-07-13 02:22:07 +02:00
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Platform *platform;
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2006-07-06 20:41:01 +02:00
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int busId;
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int deviceId;
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int functionId;
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Addr configAddr;
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public:
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PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
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2006-08-31 01:24:26 +02:00
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Platform *p);
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2006-07-06 20:41:01 +02:00
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};
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public:
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2007-07-24 06:51:38 +02:00
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typedef PciDeviceParams Params;
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const Params *
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params() const
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2006-07-06 20:41:01 +02:00
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{
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2007-07-24 06:51:38 +02:00
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return dynamic_cast<const Params *>(_params);
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}
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2004-11-13 21:45:22 +01:00
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protected:
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2007-08-16 22:49:05 +02:00
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/** The current config space. */
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2004-02-04 21:03:50 +01:00
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PCIConfig config;
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2004-05-30 23:45:46 +02:00
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/** The size of the BARs */
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2004-02-04 21:03:50 +01:00
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uint32_t BARSize[6];
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2004-05-30 23:45:46 +02:00
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/** The current address mapping of the BARs */
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2004-02-05 01:56:24 +01:00
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Addr BARAddrs[6];
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2004-02-04 21:03:50 +01:00
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2009-02-01 09:02:21 +01:00
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/** Whether the BARs are really hardwired legacy IO locations. */
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bool legacyIO[6];
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2006-08-28 19:28:31 +02:00
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/**
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* Does the given address lie within the space mapped by the given
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* base address register?
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*/
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2005-11-21 06:38:53 +01:00
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bool
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isBAR(Addr addr, int bar) const
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{
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assert(bar >= 0 && bar < 6);
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return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
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}
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2006-08-28 19:28:31 +02:00
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/**
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* Which base address register (if any) maps the given address?
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* @return The BAR number (0-5 inclusive), or -1 if none.
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*/
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2005-11-21 06:38:53 +01:00
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int
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getBAR(Addr addr)
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{
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for (int i = 0; i <= 5; ++i)
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if (isBAR(addr, i))
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return i;
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return -1;
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}
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2006-08-28 19:28:31 +02:00
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/**
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* Which base address register (if any) maps the given address?
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* @param addr The address to check.
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* @retval bar The BAR number (0-5 inclusive),
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* only valid if return value is true.
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* @retval offs The offset from the base address,
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* only valid if return value is true.
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* @return True iff address maps to a base address register's region.
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*/
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2005-11-21 06:38:53 +01:00
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bool
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2006-08-28 19:28:31 +02:00
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getBAR(Addr addr, int &bar, Addr &offs)
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2005-11-21 06:38:53 +01:00
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{
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2006-08-28 19:28:31 +02:00
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int b = getBAR(addr);
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2005-11-21 06:38:53 +01:00
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if (b < 0)
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return false;
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2006-08-28 19:28:31 +02:00
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offs = addr - BARAddrs[b];
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2005-11-21 06:38:53 +01:00
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bar = b;
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return true;
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}
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2004-11-13 21:45:22 +01:00
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protected:
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2011-10-04 11:26:03 +02:00
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Platform *platform;
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2006-04-20 23:14:30 +02:00
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Tick pioDelay;
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2006-07-06 20:41:01 +02:00
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Tick configDelay;
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2012-02-24 17:43:53 +01:00
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PciConfigPort configPort;
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2006-07-06 20:41:01 +02:00
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/**
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* Write to the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param pkt packet containing the write the offset into config space
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*/
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2006-10-20 09:10:12 +02:00
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virtual Tick writeConfig(PacketPtr pkt);
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2006-07-06 20:41:01 +02:00
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/**
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* Read from the PCI config space data that is stored locally. This may be
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* overridden by the device but at some point it will eventually call this
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* for normal operations that it does not need to override.
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* @param pkt packet containing the write the offset into config space
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*/
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2006-10-20 09:10:12 +02:00
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virtual Tick readConfig(PacketPtr pkt);
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2004-11-13 21:45:22 +01:00
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public:
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Addr pciToDma(Addr pciAddr) const
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2011-10-04 11:26:03 +02:00
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{ return platform->pciToDma(pciAddr); }
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2004-11-13 21:45:22 +01:00
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void
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intrPost()
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2011-10-04 11:26:03 +02:00
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{ platform->postPciInt(letoh(config.interruptLine)); }
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2004-11-13 21:45:22 +01:00
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void
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intrClear()
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2011-10-04 11:26:03 +02:00
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{ platform->clearPciInt(letoh(config.interruptLine)); }
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2004-11-13 21:45:22 +01:00
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2004-11-23 04:32:37 +01:00
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uint8_t
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interruptLine()
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2007-08-16 22:49:05 +02:00
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{ return letoh(config.interruptLine); }
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2004-11-23 04:32:37 +01:00
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2012-01-17 19:55:09 +01:00
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/**
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* Determine the address ranges that this device responds to.
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*
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* @return a list of non-overlapping address ranges
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2006-04-20 23:14:30 +02:00
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*/
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2012-07-09 18:35:34 +02:00
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AddrRangeList getAddrRanges() const;
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2006-04-20 23:14:30 +02:00
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2004-05-30 23:45:46 +02:00
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/**
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2004-11-13 21:45:22 +01:00
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* Constructor for PCI Dev. This function copies data from the
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* config file object PCIConfigData and registers the device with
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* a PciConfigAll object.
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2004-05-30 23:45:46 +02:00
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*/
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2007-08-16 22:49:02 +02:00
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PciDev(const Params *params);
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2004-02-05 08:25:45 +01:00
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2006-07-06 20:41:01 +02:00
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virtual void init();
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2004-02-04 21:03:50 +01:00
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2004-05-30 23:45:46 +02:00
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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2004-02-04 21:03:50 +01:00
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virtual void serialize(std::ostream &os);
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2004-05-30 23:45:46 +02:00
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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2004-02-04 21:03:50 +01:00
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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2006-07-06 20:41:01 +02:00
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2006-07-13 02:22:07 +02:00
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2012-11-02 17:32:01 +01:00
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virtual unsigned int drain(DrainManager *dm);
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2006-07-13 02:22:07 +02:00
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2012-10-15 14:12:35 +02:00
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virtual BaseSlavePort &getSlavePort(const std::string &if_name,
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PortID idx = InvalidPortID)
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2006-07-06 20:41:01 +02:00
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{
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if (if_name == "config") {
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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return configPort;
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2006-07-06 20:41:01 +02:00
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}
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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return DmaDevice::getSlavePort(if_name, idx);
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2006-07-06 20:41:01 +02:00
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}
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2004-02-04 21:03:50 +01:00
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};
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2004-11-13 21:45:22 +01:00
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#endif // __DEV_PCIDEV_HH__
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