2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-04-20 03:45:23 +02:00
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host_inst_rate 180598 # Simulator instruction rate (inst/s)
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host_mem_usage 218960 # Number of bytes of host memory used
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host_seconds 1044.69 # Real time elapsed on the host
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host_tick_rate 120412102 # Simulator tick rate (ticks/s)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-04-04 18:42:31 +02:00
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sim_insts 188669132 # Number of instructions simulated
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sim_seconds 0.125793 # Number of seconds simulated
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sim_ticks 125793203000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-04-04 18:42:31 +02:00
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system.cpu.BPredUnit.BTBHits 83359858 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 88566677 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 111813 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 9866046 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 86389460 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 110931092 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 4559844 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 9726959 # The number of times a branch was mispredicted
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.branches 40284207 # Number of branches committed
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system.cpu.commit.bw_lim_events 1785335 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.commitCommittedInsts 188683520 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 1635919 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 179794570 # The number of squashed insts skipped by commit
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::samples 224388172 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 0.840880 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 1.269231 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 118836869 52.96% 52.96% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 58355167 26.01% 78.97% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 31951737 14.24% 93.21% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 7144506 3.18% 96.39% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 2914461 1.30% 97.69% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 1962763 0.87% 98.56% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 824316 0.37% 98.93% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 613018 0.27% 99.20% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 1785335 0.80% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 224388172 # Number of insts commited each cycle
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system.cpu.commit.count 188683520 # Number of instructions committed
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system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 1848934 # Number of function calls committed.
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system.cpu.commit.int_insts 150271150 # Number of committed integer instructions.
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system.cpu.commit.loads 29852009 # Number of loads committed
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system.cpu.commit.membars 22408 # Number of memory barriers committed
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system.cpu.commit.refs 42499167 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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2011-04-04 18:42:31 +02:00
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system.cpu.committedInsts 188669132 # Number of Instructions Simulated
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system.cpu.committedInsts_total 188669132 # Number of Instructions Simulated
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system.cpu.cpi 1.333479 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.333479 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 26643 # number of LoadLockedReq accesses(hits+misses)
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.LoadLockedReq_hits 26641 # number of LoadLockedReq hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.000075 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.ReadReq_accesses 38482154 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 33506.489293 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32275.510204 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 38480613 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 51633500 # number of ReadReq miss cycles
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_miss_rate 0.000040 # miss rate for ReadReq accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.ReadReq_misses 1541 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 806 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 23722500 # number of ReadReq MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 735 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 24931 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 24931 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 31178.656598 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35098.901099 # average WriteReq mshr miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_hits 12356739 # number of WriteReq hits
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.WriteReq_miss_latency 235336500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 7548 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 38328000 # number of WriteReq MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.avg_refs 27853.817187 # Average number of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.demand_accesses 50846441 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 31573.330399 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 50837352 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 286970000 # number of demand (read+write) miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_miss_rate 0.000179 # miss rate for demand accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.demand_misses 9089 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 7262 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 62050500 # number of demand (read+write) MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.demand_mshr_misses 1827 # number of demand (read+write) MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.occ_blocks::0 1387.955871 # Average occupied blocks per context
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2011-04-20 03:45:23 +02:00
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system.cpu.dcache.occ_percent::0 0.338856 # Average percentage of cache occupancy
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_accesses 50846441 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 31573.330399 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187 # average overall mshr miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_hits 50837352 # number of overall hits
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system.cpu.dcache.overall_miss_latency 286970000 # number of overall miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_miss_rate 0.000179 # miss rate for overall accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_misses 9089 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 7262 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 62050500 # number of overall MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_mshr_misses 1827 # number of overall MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.replacements 48 # number of replacements
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system.cpu.dcache.sampled_refs 1827 # Sample count of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.tagsinuse 1387.955871 # Cycle average of tags in use
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system.cpu.dcache.total_refs 50888924 # Total number of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.writebacks 16 # number of writebacks
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2011-04-20 03:45:23 +02:00
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system.cpu.decode.BlockedCycles 36464777 # Number of cycles decode is blocked
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system.cpu.decode.BranchMispred 170249 # Number of times decode detected a branch misprediction
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system.cpu.decode.BranchResolved 17878904 # Number of times decode resolved a branch
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system.cpu.decode.DecodedInsts 446600367 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 82272510 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 104826667 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 27129630 # Number of cycles decode is squashing
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system.cpu.decode.SquashedInsts 707147 # Number of squashed instructions handled by decode
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system.cpu.decode.UnblockCycles 824217 # Number of cycles decode is unblocking
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.Branches 110931092 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 38679890 # Number of cache lines fetched
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system.cpu.fetch.Cycles 111498626 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 2123796 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 437074245 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 10106938 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.440926 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 38679890 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 87919702 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.737273 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 251517801 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.873210 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.581419 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.rateDist::0 140210227 55.75% 55.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4303837 1.71% 57.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 33014843 13.13% 70.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 15960765 6.35% 76.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 9874938 3.93% 80.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 16484434 6.55% 87.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 8406542 3.34% 90.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 5529159 2.20% 92.95% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 17733056 7.05% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.fetch.rateDist::total 251517801 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 2866910 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2464301 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 38679890 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 23669.425633 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20344.827586 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 38675903 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 94370000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000103 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 3987 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 478 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 71390000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000091 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 3509 # number of ReadReq MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.avg_refs 11021.915930 # Average number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_accesses 38679890 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 23669.425633 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 38675903 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 94370000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000103 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 3987 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 478 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 71390000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000091 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 3509 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1270.764699 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.icache.occ_percent::0 0.620491 # Average percentage of cache occupancy
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_accesses 38679890 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 23669.425633 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_hits 38675903 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 94370000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000103 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 3987 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 478 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 71390000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000091 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 3509 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.replacements 1854 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 3509 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.tagsinuse 1270.764699 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 38675903 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.idleCycles 68606 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 11160275 # Number of branch mispredicts detected at execute
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_branches 53273558 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_nop 53064 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.964190 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 53783248 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 13613267 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 19997 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 50338304 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2241625 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 4879199 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 18109550 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 368485815 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 40169981 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 7843894 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 242577015 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 4549 # Number of times the IQ has become full, causing a stall
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 2590 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 27129630 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 7356 # Number of cycles IEW is unblocking
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 954573 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 20572 # Number of memory responses ignored because the instruction is squashed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 222499 # Number of memory ordering violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 20486294 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 5462392 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_consumers 284801843 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 238885590 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.499623 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_producers 142293577 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 0.949517 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 240138833 # cumulative count of insts sent to commit
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.int_regfile_reads 542109498 # number of integer regfile reads
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.int_regfile_writes 231159216 # number of integer regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.ipc 0.749918 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.749918 # IPC: Total IPC of All Threads
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 192549438 76.89% 76.89% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 913605 0.36% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 7231 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 32771 0.01% 77.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 160968 0.06% 77.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 255770 0.10% 77.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76475 0.03% 77.47% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 457524 0.18% 77.65% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 202683 0.08% 77.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71630 0.03% 77.76% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 77.76% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 41871023 16.72% 94.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 13821469 5.52% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 250420912 # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 1881090 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 3742288 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1821838 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 2251906 # Number of floating instruction queue writes
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_busy_cnt 1580075 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.006310 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntAlu 55 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 5520 0.35% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 1266721 80.17% 80.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 307779 19.48% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 250119897 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 750424252 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 237063752 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 543997175 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 366166997 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 250420912 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 2265754 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 177594377 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 226843 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 629835 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 280770553 # Number of squashed operands that are examined and possibly removed from graph
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 251517801 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.995639 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.196239 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::0 114687732 45.60% 45.60% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 66176551 26.31% 71.91% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 44052792 17.51% 89.42% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 15274317 6.07% 95.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 7530457 2.99% 98.49% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 2838961 1.13% 99.62% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 766561 0.30% 99.92% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 123613 0.05% 99.97% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 66817 0.03% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::total 251517801 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 0.995367 # Inst issue rate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1092 # number of ReadExReq accesses(hits+misses)
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34291.512915 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31033.671587 # average ReadExReq mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 37172000 # number of ReadExReq miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.992674 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1084 # number of ReadExReq misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33640500 # number of ReadExReq MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992674 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1084 # number of ReadExReq MSHR misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 4244 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34289.280186 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.066978 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1660 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 88603500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.608860 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2584 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 79790500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605090 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2568 # number of ReadReq MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.644410 # Average number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 5336 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34289.940022 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 1668 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 125775500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.687406 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 3668 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 113431000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.684408 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 3652 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1832.230344 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 3.029186 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.055915 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.000092 # Average percentage of cache occupancy
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 5336 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34289.940022 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_hits 1668 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 125775500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.687406 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 3668 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 113431000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.684408 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 3652 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 2576 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 1835.259530 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1660 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 5314098 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 4016301 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 50338304 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 18109550 # Number of stores inserted to the mem dependence unit.
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.misc_regfile_reads 524567378 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 825084 # number of misc regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.numCycles 251586407 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.rename.BlockCycles 895052 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.CommittedMaps 180981200 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.IQFullEvents 614225 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 90974405 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 2116730 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenameLookups 956098353 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 414819410 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 416850208 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 96863032 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 27129630 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 5258013 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 235869004 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 13790121 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 942308232 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 30397669 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 2658319 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 23659926 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 2454002 # count of temporary serializing insts renamed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.rob.rob_reads 591075726 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 764090765 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1409 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
